LH521028 データシートの表示（PDF） - Sharp Electronics

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LH521028

CMOS 64K × 18 Static RAM

Sharp Electronics 

LH521028

CMOS 64K × 18 Static RAM

PIN DEFINITIONS

VCC

Positive Supply Voltage Terminals

VSS

Reference Terminals

A0 – A15 Address Bus

Input

The Address bus is decoded to select one 18-bit word

out of the total 64K words for Read and Write operations.

E

Chip Enable

Active LOW Input

Chip Enable is used to enable the device for Read and

Write operations. When HIGH, both Read and Write

operations are disabled and the device is in a reduced

power state. When LOW, a Read or Write operation is

enabled.

W

Write Enable Active LOW Input

Write Enable is used to select either Read or Write

operations when the device is enabled. When Write

Enable is HIGH and the device is Enabled, a Read

operation is selected. When Write Enable is LOW and the

device is enabled, a Write operation is selected. A Byte-

write operation is available by using the Byte-select con-

trols.

SH, SL Select High

Select Low

Active LOW Inputs

The Select High and Select Low signals, in conjunction

with the Chip Enable and Write Enable signals, allow the

selection of the individual bytes for Read and Write op-

erations. When High, the Select signal will deselect its

byte and prevent Read or Write operations. When the

Select signal is LOW andChip Enable is LOW, a Read or

Write operation is performed at the location determined

by the contents of the Address bus. When Chip Enable is

HIGH, the Select signals are Don’t Care. Select Low (SL)

is assigned to DQ0 – DQ8 and Select High (SH) is

assigned to DQ9 – DQ17.

ALE

Address Latch Active High Input

Enable

The Address Latch Enable signal is used to control the

Transparent latches on the Address bus. The Latches are

transparent when HIGH and are latched when LOW. If

not required, Address Latch Enable may be tied HIGH,

leaving the Address bus in a transparent condition.

DQ0 – DQ17 Data Bus

Input/Output

DQ0 – DQ8 comprise the Low byte, selected by SL,

and DQ9 – DQ17 comprise the High Data byte, selected

by SH. The Data Bus is in a high impedance input mode

during Write operations and standby. The Data bus is in

a low-impedance output mode during Read operations.

G

Output Enable Active LOW Input

The Output Enable signal is used to control the output

buffers on the Data Input/Output bus. When G is HIGH,

all output buffers are forced to a high impedance condi-

tion. When G is LOW, the output buffers will become

active only during a Read operation (E and SH / SL are

LOW, W is HIGH).

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