M66281FP データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M66281FP

5120 x 8-BIT x 2 LINE MEMORY

MITSUBISHI ELECTRIC  

MITSUBISHI <DIGITAL ASSP>

M66281FP

5120 x 8-BIT x 2 LINE MEMORY

• n-bit delay 2

(Slides input timings of WRESB and RRESB at cycles according to the delay length.)

0 cycle 1 cycle

WCK

RCK

tRESS tRESH

WRESB

2 cycle n-2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle

RRESB

Dn

tDS tDH

(0)

(1)

tRESS tRESH

tDS tDH

(2)

(n-2)

(n-1)

(n)

(n+1)

(n+2)

(n+3)

Q0n

(Q1n)

m cycle

tAC

tOH

(0)

(1)

(2)

(3)

WEB, REB = "L"

m≥3

• n-bit delay 3

(Slides address by disabling REB in the period according to the delay length.)

0 cycle 1 cycle 2 cycle

WCK

RCK

tRESS tRESH

WRESB

RRESB

REB

Dn

tDS tDH

(0)

(1)

(2)

n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle

tNREH tRES

(n-2)

(n-1)

tDS tDH

(n)

(n+1)

(n+2)

(n+3)

Q0n

(Q1n)

HIGH-Z

m cycle

tAC

tOH

invalid

(1)

(2)

(3)

WEB = "L"

m≥3

11

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