M50LPW002 データシートの表示（PDF） - STMicroelectronics

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M50LPW002

2 Mbit (256Kb x8, Boot Block) 3V Supply Low Pin Count Flash Memory

STMicroelectronics 

M50LPW002

Table 6. Bus Write Field Definitions (LPC Interface)

Clock Clock

Cycle Cycle

Number Count

Field

LAD0-

LAD3

Memory

I/O

Description

On the rising edge of CLK with LFRAME Low, the contents

1

1

START 0000b

I

of LAD0-LAD3 must be 0000b to indicate the start of a LPC

cycle.

CYCTY

Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

2

1

PE +

011Xb

I

indicates the direction of transfer: 1b for write. Bit 0 is don’t

DIR

care (X).

3-10

8

ADDR

XXXX

A 32-bit address phase is transferred starting with the most

I

significant nibble first. A23-A31 must be set to 1. A22 = 1 for

Array, A22 = 0 for registers access. For A18-A21 values,

refer to Table 3.

11-12

2

DATA

XXXX

I

Data transfer is two cycles, starting with the least significant

nibble.

13

1

TAR

1111b

I

The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

14

1

TAR

1111b

(float)

O

The LPC Flash Memory takes control of LAD0-LAD3 during

this cycle.

15

1

SYNC

0000b

O

The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.

16

1

TAR

1111b

O

The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.

17

1

TAR

1111b

(float)

N/A

The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

Figure 6. Bus Write Waveforms (LPC Interface)

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START

1

CYCTYPE

+ DIR

1

ADDR

8

DATA

2

TAR

2

SYNC

1

TAR

2

AI04430

11/39

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