M50LPW080N データシートの表示（PDF） - STMicroelectronics

部品番号

コンポーネント説明

メーカー

M50LPW080N

8 Mbit (1M x8, Uniform Block) 3V Supply Low Pin Count Flash Memory

STMicroelectronics 

M50LPW080

Write Protect, WP, does not affect the protection of

the Top Block (Block 15).

Write Protect, WP, must be set prior to a Program

or Block Erase operation is initiated and must not

be changed until the operation completes or un-

predictable results may occur. Care should be tak-

en to avoid unpredictable behavior by changing

WP during Program or Erase Suspend.

Reserved for Future Use (RFU). These pins do

not have assigned functions in this revision of the

part. They must be left disconnected.

Table 4. Block Addresses

Size

(Kbytes)

Address Range

Block

Number

Block Type

64 F0000h-FFFFFh 15

Top Block

64 E0000h-EFFFFh 14

Main Block

64 D0000h-DFFFFh 13

Main Block

64 C0000h-CFFFFh 12

Main Block

64 B0000h-BFFFFh 11

Main Block

64 A0000h-AFFFFh 10

Main Block

64 90000h-9FFFFh

9

Main Block

64 80000h-8FFFFh

8

Main Block

64 70000h-7FFFFh

7

Main Block

64 60000h-6FFFFh

6

Main Block

64 50000h-5FFFFh

5

Main Block

64 40000h-4FFFFh

4

Main Block

64 30000h-3FFFFh

3

Main Block

64 20000h-2FFFFh

2

Main Block

64 10000h-1FFFFh

1

Main Block

64 00000h-0FFFFh

0

Main Block

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

For the Address/Address Multiplexed (A/A Mux)

Interface see Figure 3. and Table 2..

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A19). They are

latched during any bus operation by the Row/Col-

umn Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs hold the data that is written to or read

from the memory. They output the data stored at

the selected address during a Bus Read opera-

tion. During Bus Write operations they represent

the commands sent to the Command Interface of

the internal state machine. The Data Inputs/Out-

puts, DQ0-DQ7, are latched during a Bus Write

operation.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Row/Column Address Select (RC). The Row/

Column Address Select input selects whether the

Address Inputs should be latched into the Row Ad-

dress bits (A0-A10) or the Column Address bits

(A11-A19). The Row Address bits are latched on

the falling edge of RC whereas the Column Ad-

dress bits are latched on the rising edge.

Ready/Busy Output (RB). The Ready/Busy pin

gives the status of the memory’s Program/Erase

Controller. When Ready/Busy is Low, VOL, the

memory is busy with a Program or Erase operation

and it will not accept any additional Program or

Erase command except the Program/Erase Sus-

pend command. When Ready/Busy is High, VOH,

the memory is ready for any Read, Program or

Erase operation.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid. After VCC

becomes valid the Command Interface is reset to

Read mode.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pins and the VSS Ground

pin to decouple the current surges from the power

supply. Both VCC Supply Voltage pins must be

connected to the power supply. The PCB track

widths must be sufficient to carry the currents re-

quired during program and erase operations.

VPP Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Pro-

gram (see the Quadruple Byte Program Command

description) and Fast Erase options of the memory

and to protect the memory. When VPP < VPPLK

Program and Erase operations cannot be per-

formed and an error is reported in the Status Reg-

ister if an attempt to change the memory contents

is made. When VPP = VCC Program and Erase op-

erations take place as normal. When VPP = VPPH

Fast Program (if a Quadruple Byte Program Com-

mand is performed) and Fast Erase operations are

11/44

Share Link: