M58BV016DB7T3F データシートの表示（PDF） - Micron Technology

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M58BV016DB7T3F

16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories

Micron Technology 

Signal descriptions

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

2

Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A18)

The address inputs are used to select the cells to access in the memory array during bus

operations either to read or to program data. During bus write operations they control the

commands sent to the command interface of the program/erase controller. Chip Enable

must be Low when selecting the addresses.

The address inputs are latched on the rising edge of Latch Enable L or Burst Clock K,

whichever occurs first, in a read operation.The address inputs are latched on the rising edge

of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a write operation.

The address latch is transparent when Latch Enable is Low, VIL. The address is internally

latched in an erase or program operation.

2.2

Data inputs/outputs (DQ0-DQ31)

The data inputs/outputs output the data stored at the selected address during a bus read

operation, or are used to input the data during a program operation. During bus write

operations they represent the commands sent to the command interface of the

program/erase controller. When used to input data or write commands they are latched on

the rising edge of Write Enable or Chip Enable, whichever occurs first.

When Chip Enable and Output Enable are both Low, VIL, and Output Disable is at VIH, the

data bus outputs data from the memory array, the electronic signature, the CFI information

or the contents of the status register. The data bus is high impedance when the device is

deselected with Chip Enable at VIH, Output Enable at VIH, Output Disable at VIL or

Reset/Power-down at VIL. The status register content is output on DQ0-DQ7 and DQ8-

DQ31 are at VIL.

2.3

Chip Enable (E)

The Chip Enable, E, input activates the memory control logic, input buffers, decoders and

sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power

consumption to the standby level.

2.4

Output Enable (G)

The Output Enable, G, gates the outputs through the data output buffers during a read

operation, when Output Disable GD is at VIH. When Output Enable G is at VIH, the outputs

are high impedance independently of Output Disable.

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