M58BV016DB7T3F データシートの表示（PDF） - Micron Technology
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M58BV016DB7T3F Datasheet PDF : 70 Pages
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Bus operations
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
3.1.7
3.1.8
3.1.9
3.1.10
Standby mode
When Chip Enable is High, VIH, and the Program/Erase controller is idle, the memory enters
Standby mode, the power consumption is reduced to the standby level and the Data
inputs/outputs pins are placed in the high impedance state regardless of Output Enable,
Write Enable or Output Disable inputs.
Automatic low power mode
If there is no change in the state of the bus for a short period of time during asynchronous
bus read operations the memory enters auto low power mode where the internal supply
current is reduced to the auto-standby supply current. The data inputs/outputs will still
output data if a bus read operation is in progress.
Automatic low power is only available in asynchronous read modes.
Power-down mode
The memory is in power-down when Reset/Power-down, RP, is at VIL. The power
consumption is reduced to the power-down level and the outputs are high impedance,
independent of the Chip Enable, E, Output Enable, G, Output Disable, GD, or Write Enable,
W, inputs.
Electronic signature
Two codes identifying the manufacturer and the device can be read from the memory
allowing programming equipment or applications to automatically match their interface to
the characteristics of the memory. The electronic signature is output by giving the Read
Electronic Signature command. The manufacturer code is output when all the address
inputs are at VIL. The device code is output when A1 is at VIH and all the other address pins
are at VIL (see Table 5: Asynchronous read electronic signature operation). Issue a Read
Memory Array command to return to read mode.
Table 4. Asynchronous bus operations(1)
Bus operation
Step
E G GD W RP L A0-A18 DQ0-DQ31
Asynchronous bus read
VIL VIL VIH VIH VIH VIL Address Data output
Asynchronous latch
controlled bus read
Address Latch VIL VIH VIH VIL VIH VIL Address High-Z
Read
VIL VIL VIH VIH VIH VIH
X
Data output
Asynchronous page read
VIL VIL VIH VIH VIH X Address Data output
Asynchronous bus write
VIL VIH X VIL VIH VIL Address Data input
Asynchronous latch
controlled bus write
Address Latch VIL VIL VIH VIH VIH VIL Address High-Z
Write
VIL VIH X VIL VIH VIH
X
Data input
Output Enable, G
VIL VIH VIH VIH VIH X
X
High-Z
Output Disable, GD
VIL VIL VIL VIH VIH X
X
High-Z
Standby
VIH X X X VIH X
X
High-Z
Reset/power-down
X X X X VIL X
X
High-Z
1. X = don’t care.
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