M58MR016C データシートの表示（PDF） - STMicroelectronics

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M58MR016C

16 Mbit (1Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58MR016C, M58MR016D

figuration Register (A19-A16 are don’t care). At

Power-up the Read Configuration Register is set

to asynchronous Read mode, Power-down dis-

abled and bus invert (power save function) dis-

abled. A description of the effects of each

configuration bit is given in Table 14.

Read mode (CR15). The device supports an

asynchronous page mode and a synchronous

burst mode. In asynchronous page mode, the de-

fault at power-up, data is internally read and stored

in a buffer of 4 words selected by ADQ0 and ADQ1

address inputs. In synchronous burst mode, the

device latches the starting address and then out-

puts a sequence of data that depends on the Read

Configuration Register settings (see Figures 10,

11 and 12).

Synchronous burst mode is supported in both pa-

rameter and main blocks; it is also possible to per-

form burst mode read across the banks.

Bus Invert configuration (CR14). This register

bit is used to enable the BINV pin functionality.

BINV functionality depends upon configuration

bits CR14 and CR15 (see Table 14 for configura-

tion bits definition) as shown in Table 15. As output

pin BINV is active only when enabled (CR14 = 1)

in Read Array burst mode (CR15 = 0). As input pin

BINV is active only when enabled (CR14 = 1).

BINV is ignored when ADQ0-ADQ15 lines are

used as address inputs (addresses must not be in-

verted).

X-Latency (CR13-CR11). These configuration

bits define the number of clock cycles elapsing

from L going low to valid data available in burst

mode (see Figure 6). The correspondence be-

tween X-Latency settings and the maximum sus-

tainable frequency must be calculated taking into

account some system parameters.

Two conditions must be satisfied:

– (n + 2) tK ≥ tACC + tQVK_CPU + tAVK_CPU

– tK > tKQV + tQVK_CPU

where "n" is the chosen X-Latency configuration

code, tK is the clock period, tAVK_CPU is the ad-

dress setup time guaranteed by the system CPU,

and tQVK_CPU is the data setup time required by

the system CPU.

Power-down configuration (CR10). The RP pin

may be configured to give very low power con-

sumption when driven low (power-down state). In

power-down the ICC supply current is reduced to a

typical figure of ICC2; if this function is disabled

(default at power-up) the RP pin causes only a re-

set of the device and the supply current is the

stand-by value. The recovery time after a RP pulse

is significantly longer when power-down is en-

abled (see Table 31).

Wait configuration (CR8). In burst mode WAIT

indicates whether the data on the output bus are

valid or a wait state must be inserted. The config-

18/51

uration bit determines if WAIT will be asserted one

clock cycle before the wait state or during the wait

state (see Figure 7). WAIT is asserted during a

continuous burst and also during a 4 or 8 burst

length if no-wrap configuration is selected.

Burst order configuration (CR7) and Burst

Wrap configuration (CR3). See Table 16 for

burst order and length.

Clock configuration (CR6). In burst mode deter-

mines if address is latched and data is output on

the rising or falling edge of the clock.

Burst length (CR2-CR0). In burst mode deter-

mines the number of words output by the memory.

It is possible to have 4 words, 8 words or a contin-

uous burst mode, in which all the words are read

sequentially. In continuous burst mode the burst

sequence can cross the end of each of the two

banks (all banks in read array mode). In continu-

ous burst mode or in 4, 8 words no-wrap it may

happen that the memory will stop the data output

flow for a few clock cycles; this event is signaled by

WAIT going low until the output flow is resumed.

The initial address determines if the output delay

will occur as well as its duration. If the starting ad-

dress is aligned to a four words boundary no wait

states will be needed. If the starting address is

shifted by 1,2 or 3 positions from the four word

boundary, WAIT will be asserted for 1, 2 or 3 clock

cycles when the burst sequence is crossing the

first 64 word boundary. WAIT will be asserted only

once during a continuous burst access. See also

Table 16.

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