M58MR032-ZCT データシートの表示（PDF） - STMicroelectronics

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M58MR032-ZCT

32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory

STMicroelectronics 

M58MR032C, M58MR032D

Note: 1. First cycle command address should be the same as the operation’s target address. The first cycle of the RD, RSR, RSIG or RCFI

instruction is followed by read operations in the bank array or special register. Any number of read cycles can occur after one com-

mand cycle.

2. BKA means Address within the bank;

BA means Block Address;

EA means Electronic Signature Address;

CA means Common Flash Interface Address;

WA means Word Address;

PA means Protection Register Address (see Table 7);

LPA means Lock Protection Register Address (see Table 7);

RCA means Read Configuration Register Address.

3. PD means Protection Data;

CD means Common Flash Interface Data;

ED means Electronic Signature Data;

WD means Data to be programmed at the address location WA;

LPD means Lock protection Register Data

4. WA1, WA2, WA3 and WA4 must be consecutive address differing only for address bits A1-A0.

5. Read cycle after e CLSR instruction will output the memory array.

CFI Query (RCFI)

The CFI Query Mode is associated to bank A. The

address of the first write cycle must be within the

bank A. The status of the other bank is not affected

by the command (see Table 8). Writing 98h the de-

vice enters the Common Flash Interface Query

mode. Next read operations in the bank A will read

the CFI data. Write a read instruction to return to

Read mode (refer to the Common Flash Interface

section).

Clear Status Register (CLSR)

The Clear Status Register uses a single write op-

eration, which resets bits b1, b3, b4 e b5 of the sta-

tus register. The Clear Status Register is executed

writing the command 50h independently of the ap-

plied VPP voltage. After executing this command

the device returns to read array mode. The Clear

Status Register command clears only the status

register of the addressed bank.

Block Erase (EE)

Block erasure sets all the bits within the selected

block to ’1’. One block at a time can be erased. It

is not necessary to pre-program the block as the

P/E.C. will do it automatically before erasing. This

instruction use two writes cycles. The first com-

mand written is the Block Erase Set up command

20h. The second command is the Erase Confirm

command D0h. An address within the block to be

erased should be given to the memory during the

two cycles command. If the second command giv-

en is not an erase confirm, the status register bits

b4 and b5 are set and the instruction aborts.

After writing the command, the device outputs sta-

tus register data when any address within the bank

is read. At the end of the operation the bank will re-

main in read status register until a read array com-

mand is written.

Status Register bit b7 is ’0’ while the erasure is in

progress and ’1’ when it has completed. After com-

pletion the Status Register bit b5 returns ’1’ if there

has been an Erase Failure. Status register bit b1

returns ’1’ if the user is attempting to erase a pro-

tected block. Status Register bit b3 returns a ’1’ if

VPP is below VPPLK. Erase aborts if RP turns to

VIL. As data integrity cannot be guaranteed when

the erase operation is aborted, the erase must be

repeated (see Table 12). A Clear Status Register

instruction must be issued to reset b1, b3, b4 and

b5 of the Status Register. During the execution of

the erase by the P/E.C., the bank with the block in

erase accepts only the RSR (Read Status Regis-

ter) and PES (Program/Erase Suspend) instruc-

tions. See figure 19 for Erase Flowchart and

Pseudo Code.

Bank Erase (BE)

Bank erase sets all the bits within the selected

bank to ’1’. It is not necessary to pre-program the

block as the P/E.C. will do it automatically before

erasing.

This instruction uses two writes cycles. The first

command written is the Bank Erase set-up com-

mand 80h. The second command is the Erase

Confirm command D0h. An address within the

bank to be erased should be given to the memory

during the two cycles command. See the Block

Erase command section for status register bit de-

tails.

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