MACH230-18JI データシートの表示（PDF） - Lattice Semiconductor

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MACH230-18JI

High-Density EE CMOS Programmable Logic

Lattice Semiconductor 

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued)

Parameter

Symbol

Parameter Description

-10

Min Max Unit

tIGS

Input Latch Gate to Output Latch Setup

11

ns

tWIGL

Input Latch Gate Width LOW

4

ns

tPDLL

Input, I/O, or Feedback to Output Through Transparent

Input and Output Latches

16

ns

tAR

Asynchronous Reset to Registered or Latched Output

18

ns

tARW

Asynchronous Reset Width

10

ns

tARR

Asynchronous Reset Recovery Time

10

ns

tAP

Asynchronous Preset to Registered or Latched Output

18

ns

tAPW

Asynchronous Preset Width

10

ns

tAPR

Asynchronous Preset Recovery Time

10

ns

tEA

Input, I/O, or Feedback to Output Enable

15

ns

tER

Input, I/O, or Feedback to Output Disable

15

ns

Note:

1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the designis modified where

capacitance may be affected.

10

MACH230-10 (Com’l)

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