MACH4-96 データシートの表示（PDF） - Lattice Semiconductor

部品番号

コンポーネント説明

メーカー

MACH4-96

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

VANTIS

Individual

Output Enable

Product Term

From Output

Switch Matrix

To Input

Switch

Matrix

Q D/L*

Block CLK0

Block CLK1

Block CLK2

Block CLK3

Figure 6. I/O Cell

21535A-6

SpeedLocking for Guaranteed Fixed Timing

The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell

with the assistance of an XOR gate without incurring additional timing delays. Using this

architectural strength, the M4-96/96 provides the industry’s highest-speed and only fixed timing

at 5-V supply voltages. This SpeedLocking feature delivers guaranteed fixed speed independent

of logic path, routing resources, or design refits.

5-V In-System Programming

Another benefit of the JTAG circuitry is the ability to use the JTAG port for 5-V programming.

This allows the device to be soldered to the board before programming. Once the device is

attached, the delicate Plastic Quad Flat Pack, or PQFP, leads are protected from programming

and testing operations that could potentially damage them. Programming and verification of the

device is done serially which is ideal for on-board programming since it only requires the use

of the Test Access Port. There is an optional ENABLE pin which can be used to inhibit

programming for additional security. These devices can be programmed in any JTAG chain.

JTAG Boundary Scan Testing

JTAG is the commonly used acronym for the IEEE Standard 1149.1-1990. The JTAG standard

defines input and output pins, logic control functions, and instructions. Vantis has incorporated

this standard into the M4-96/96 device.

12

MACH4-96/96-15

Share Link: