MACH4-96 データシートの表示（PDF） - Lattice Semiconductor

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MACH4-96

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

VANTIS

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) (Continued)

Parameter Symbol

Parameter Description

tGWA

Product Term Gate Width LOW (for LOW transparent) or HIGH (for

HIGH transparent)

tSLS

Setup Time from Input, I/O, or Feedback to Global Gate

tHLS

Latch Data Hold Time Using Global Gate

tGOS

Gate to Output (Note 2)

tGWS

Global Gate Width LOW (for LOW transparent) or HIGH (for HIGH

transparent)

-15

Min

Max

Unit

9

ns

10

ns

0

ns

11

ns

6

ns

tPDL

Input, I/O or Feedback to Output through Transparent Output Latch

17

ns

tAR

Asynchronous Reset to Registered or Latched Output

20

ns

tARW

Asynchronous Reset Width (Note 3)

15

ns

tARR

Asynchronous Reset Recovery Time (Note 3)

15

ns

tAP

Asynchronous Preset to Registered or Latched Output

20

ns

tAPW

Asynchronous Preset Width (Note 3)

15

ns

tAPR

Asynchronous Preset Recovery Time (Note 3)

15

ns

tEA

Input, I/O, or Feedback to Output Enable (Note 2)

2

15

ns

tER

Input, I/O, or Feedback to Output Disable (Note 2

2

15

ns

Notes:

1. See Switching Test Circuit at the end of this Data Book for test conditions.

2. Parameters measured with 32 outputs switching.

3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where

frequency may be affected.

4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.

16

MACH4-96/96-15 (Com’l)

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