MCM72FB8ML7.5R データシートの表示（PDF） - Motorola => Freescale

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MCM72FB8ML7.5R

256K x 72 Bit BurstRAM Multichip Module

Motorola => Freescale 

K

ADSC

STOP CLOCK WITH DESELECT OPERATION TIMING

SE1

DATA IN

VIH OR VIL FIXED (SEE NOTE 1)

DQx

DATA

DATA

HIGH–Z

CONTINUE

BURST READ

CLOCK STOP

(DESELECTED)

WAKE UP

(DESELECTED)

NOTES:

1. While the clock is stopped, DATA IN must be fixed in a high (VIH) or low (VIL) state to reduce the DC current of the

input buffers. For lowest power operation, all data and address lines should be held in a low (VIL) state and control

lines held in an inactive state.

2. For best possible power savings, the data–in should be driven low.

MOTOROLA FAST SRAM

MCM72FB8ML  MCM72PB8ML

17

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