MCM72FB8ML7.5R データシートの表示（PDF） - Motorola => Freescale
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MCM72FB8ML7.5R Datasheet PDF : 20 Pages
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NON–BURST SYNCHRONOUS OPERATION
Although this BurstRAM has been designed for PowerPC–
based and other high end MPU–based systems, these
SRAMs can be used in other high speed L2 cache or
memory applications that do not require the burst address
feature. Most L2 caches designed with a synchronous inter-
face can make use of the MCM72FB8ML or MCM72PB8ML.
The burst counter feature of the BurstRAM can be disabled,
and the SRAM can be configured to act upon a continuous
stream of addresses. See Figures 5 and 6.
CONTROL PIN TIE VALUES (H ≥ VIH, L ≤ VIL)
Non–Burst
ADSP ADSC ADV SE1 LBO
Sync Non–Burst,
Pipelined SRAM
H
L
H
L
X
NOTE: Although X is specified in the table as a don’t care, the pin
must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 5. Configured as Non–Burst Synchronous Flow–Through SRAM
K
ADDR
A
B
C
D
W
E
F
G
H
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 6. Configured as Non–Burst Synchronous Pipelined SRAM
MCM72FB8ML MCM72PB8ML
18
MOTOROLA FAST SRAM
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