ORT8850 データシートの表示（PDF） - Lattice Semiconductor

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ORT8850

Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver

Lattice Semiconductor 

Lattice Semiconductor

ORCA ORT8850 Data Sheet

• New 200 MHz embedded quad-port RAM blocks, two read ports, two write ports, and two sets of byte lane

enables. Each embedded RAM block can be configured as:

– One—512 x 18 (quad-port, two read/two write) with optional built-in arbitration.

– One—256 x 36 (dual-port, one read/one write).

– One—1K x 9 (dual-port, one read/one write).

– Two—512 x 9 (dual-port, one read/one write for each).

– Two RAM with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).

– Supports joining of RAM blocks.

– Two 16 x 8-bit Content Addressable Memory (CAM) support.

– FIFO 512 x 18, 256 x 36, 1K x 9, or dual 512 x 9.

– Constant multiply (8 x 16 or 16 x 8).

– Dual variable multiply (8 x 8).

• Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),

embedded RAM blocks, and embedded backplane transceiver blocks with 100 MHz bus performance. Included

are built-in system registers that act as the control and status center for the device.

• Built-in testability:

– Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG).

– Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7.

– TS_ALL testability function to 3-state all I/O pins.

– New temperature-sensing diode.

• Cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. This

feature also supports compliance with many setup/hold and clock to out I/O specifications and may provide

reduced ground bounce for output buses by allowing flexible delays of switching output buffers.

Programmable Logic System Features

• PCI local bus compliant for FPGA I/Os.

• Improved PowerPC/Power QUICC MPC860 and PowerPC II MPC8260 high-speed synchronous MicroProcessor

Interface can be used for configuration, readback, device control, and device status, as well as for a general-pur-

pose interface to the FPGA logic, RAMs, and embedded backplane transceiver blocks. Glueless interface to syn-

chronous PowerPC processors with user-configurable address space provided.

• New embedded AMBA™ specification 2.0 AHB system bus (ARM ® processor) facilitates communication among

the MicroProcessor Interface, configuration logic, embedded block RAM, FPGA logic, and backplane transceiver

logic.

• New network PLLs meet ITU-T G.811 specifications and provide clock conditioning for DS-1/E-1 and STS-

3/STM-1 applications.

• Variable size bused readback of configuration data capability with the built-in MicroProcessor Interface and sys-

tem bus.

• Internal, 3-state, and bidirectional buses with simple control provided by the SLIC.

• New clock routing structures for global and local clocking significantly increases speed and reduces skew (<200

ps for OR4E04).

• New local clock routing structures allow creation of localized clock trees.

• Two new edge clock routing structures allow up to six high-speed clocks on each edge of the device for improved

setup/hold and clock-to-out performance.

• New Double-Data Rate (DDR) and Zero-Bus Turn-around (ZBT) memory interfaces support the latest high-

speed memory interfaces.

• New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal

logic.

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