P89LPC932A1 データシートの表示（PDF） - NXP Semiconductors.

部品番号

コンポーネント説明

メーカー

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

Table 5. Number of I/O pins available …continued

Clock source

Reset option

External clock input

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power-up)

External RST pin supported[1]

No external reset (except during power-up)

External RST pin supported[1]

Number of I/O pins

(28-pin package)

25

24

24

23

[1] Required for operation above 12 MHz.

7.13.1 Port configurations

All but three I/O port pins on the P89LPC932A1 may be configured by software to one of

four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two configuration registers for each port

select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be configured.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or

open-drain.

7.13.1.1 Quasi-bidirectional output configuration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-drain output except that there are three pull-up transistors in

the quasi-bidirectional output that serve different purposes.

The P89LPC932A1 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional

mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD,

causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is

discouraged.

A quasi-bidirectional port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

7.13.1.2 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port configured in this manner must have an external pull-up, typically a resistor

tied to VDD.

An open-drain port pin has a Schmitt trigger input that also has a glitch suppression

circuit.

7.13.1.3 Input-only configuration

The input-only port configuration has no output drivers. It is a Schmitt trigger input that

also has a glitch suppression circuit.

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

22 of 64

Share Link: