P89LPC932A1 データシートの表示（PDF） - NXP Semiconductors.

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P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

For correct activation of brownout detect, the VDD rise and fall times must be observed.

Please see Table 8 “Static characteristics” for specifications.

7.14.2 Power-on detection

The Power-on detect has a function similar to the brownout detect, but is designed to work

as power comes up initially, before the power supply voltage reaches a level where

brownout detect can work. The POF flag in the RSTSRC register is set to indicate an

initial power-up condition. The POF flag will remain set until cleared by software.

7.15 Power reduction modes

The P89LPC932A1 supports three different power reduction modes. These modes are

Idle mode, Power-down mode, and Total Power-down mode.

7.15.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor

when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle

mode.

7.15.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The

P89LPC932A1 exits Power-down mode via any reset, or certain interrupts. In Power-down

mode, the power supply voltage may be reduced to the data retention voltage VDDR. This

retains the RAM contents at the point where Power-down mode was entered. SFR

contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly

recommended to wake up the processor via reset in this case. VDD must be raised to

within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: Brownout detect,

watchdog timer, Comparators (note that Comparators can be powered-down separately),

and RTC/System Timer. The internal RC oscillator is disabled unless both the RC

oscillator has been selected as the system clock and the RTC is enabled.

7.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

7.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, The RPE selection is overridden and this pin will

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

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