PCA9574 データシートの表示（PDF） - NXP Semiconductors.

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PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

NXP Semiconductors. 

NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO

7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register

Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.

Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the

pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.

Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.

Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 3. Setting

the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register 3

will have no effect on the I/O.

Table 7. Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit

description

Legend: * default value.

Bit Symbol Access Value Description

7 E0.7

R/W

X

not used

6 E0.6

R/W

X

5 E0.5

R/W

X

4 E0.4

R/W

X

3 E0.3

R/W

X

2 E0.2

R/W

X

1 E0.1

R/W

0*

allows the user to enable/disable pull-up/pull-downs on the

I/O pins

0 = disables pull-up/pull-downs on the I/O pins and

contents of Register 3 will have no effect on the I/O

(default value)

1 = enables selection of pull-up/pull-down using

Register 3

0 E0.0

R/W

0*

allows user to enable/disable the bus-hold feature for the I/O

pins

0 = disables bus-hold feature (default value)

1 = enables bus-hold feature

PCA9574_2

Product data sheet

Rev. 02 — 27 July 2009

© NXP B.V. 2009. All rights reserved.

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