PLS159 データシートの表示（PDF） - Philips Electronics

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PLS159

Programmable logic sequencer (16 × 45 × 12)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic sequencer

(16 × 45 × 12)

Product specification

PLS159A

TIMING DIAGRAMS

I, B

(INPUTS)

CLK

F

(OUTPUTS)

OE

1.5V

1.5V

tIH1

tIS1

1.5V

tIS1

1.5V

1.5V

tCKH

tCKL

tCKP

1.5V

VT

tCKO

tOD1

1.5V

1.5V

tOE1

Flip-Flop Outputs

+3V

0V

+3V

0V

VOH

VOL

+3V

0V

I, B

(INPUTS)

1.5V

B

(OUTPUTS)

I, B

(OUTPUT

ENABLE)

ÇÇÇÇtPDÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ1.5V

tOE2

+1.5V

Gate Outputs

tOD2

+1.5V

+3V

0V

VOH

VT

VOL

+3V

0V

+5V

ÇÇÇÇÇ VCC

ÇÇÇÇÇÇÇÇÇÇ F

ÇÇÇÇÇÇÇÇÇÇ (OUTPUTS)

4.5V

tPPR

1.5V

1.5V

tCKO

0V

VOH

VOL

+3V

I, B

(INPUTS)

1.5V

1.5V

0V

tIH1

tIS1

+3V

CLK

1.5V

1.5V

1.5V

0V

tIS1

tCKH

tCKL

tCKP

Power-On Reset

TIMING DEFINITIONS

SYMBOL PARAMETER

tCKH

tCKL

tCKP

tPRH

tIS1

Width of input clock pulse.

Interval between clock pulses.

Clock period.

Width of preset input pulse.

Required delay between

beginning of valid input and

positive transition of clock.

Required delay between

tIS2

beginning of valid input forced

at flip-flop output pins, and

positive transition of clock.

Required delay between

tIH1

positive transition of clock and

end of valid input data.

Required delay between

tIH2

positive transition of clock and

end of valid input data forced

at flip-flop output pins.

tCKO

Delay between positive

transition of clock and when

outputs become valid (with

OE Low).

Delay between beginning of

tOE1

Output Enable Low and when

outputs become valid.

Delay between beginning of

tOD1

Output Enable High and

when outputs are in the

OFF-State.

Delay between VCC (after

tPPR

power-on) and when flip-flop

outputs become preset at “1”

(internal Q outputs at “0”).

Propagation delay between

tPD

combinational inputs and

outputs.

Delay between predefined

tOE2

Output Enable High, and

when combinational outputs

become valid.

Delay between predefined

tOD2

Output Enable Low and when

combinational outputs are in

the OFF-State.

tPRO

Delay between positive

transition of predefined

Preset/Reset input, and

when flip-flop outputs become

valid.

October 22, 1993

31

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