28F008SA データシートの表示（PDF） - Intel

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28F008SA

8-MBIT (1-MBIT x 8) FlashFile™ MEMORY

Intel 

28F008SA

VCC VPP RP Transitions and the

Command Status Registers

Byte write and block erase completion are not guar-

anteed if VPP drops below VPPH If the VPP Status bit

of the Status Register (SR 3) is set to ‘‘1’’ a Clear

Status Register command MUST be issued before

further byte write block erase attempts are allowed

by the WSM Otherwise the Byte Write (SR 4) or

Erase (SR 5) Status bits of the Status Register will

be set to ‘‘1’’s if error is detected RP transitions to

VIL during byte write and block erase also abort the

operations Data is partially altered in either case

and the command sequence must be repeated after

normal operation is restored Device poweroff or

RP transitions to VIL clear the Status Register to

initial value 10000 for the upper 5 bits

The Command User Interface latches commands as

issued by system software and is not altered by VPP

or CE transitions or WSM actions Its state upon

powerup after exit from deep powerdown or after

VCC transitions below VLKO is Read Array Mode

After byte write or block erase is complete even

after VPP transitions down to VPPL the Command

User Interface must be reset to Read Array mode via

the Read Array command if access to the memory

array is desired

Power Up Down Protection

The 28F008SA is designed to offer protection

against accidental block erasure or byte writing dur-

ing power transitions Upon power-up the

28F008SA is indifferent as to which power supply

VPP or VCC powers up first Power supply sequenc-

ing is not required Internal circuitry in the 28F008SA

ensures that the Command User Interface is reset to

the Read Array mode on power up

A system designer must guard against spurious

writes for VCC voltages above VLKO when VPP is

active Since both WE and CE must be low for a

command write driving either to VIH will inhibit

writes The Command User Interface architecture

provides an added level of protection since altera-

tion of memory contents only occurs after success-

ful completion of the two-step command sequences

Finally the device is disabled until RP is brought to

VIH regardless of the state of its control inputs This

provides an additional level of memory protection

Power Dissipation

When designing portable systems designers must

consider battery power consumption not only during

device operation but also for data retention during

system idle time Flash nonvolatility increases us-

able battery life because the 28F008SA does not

consume any power to retain code or data when the

system is off

In addition the 28F008SA’s deep powerdown mode

ensures extremely low power dissipation even when

system power is applied For example portable PCs

and other power sensitive applications using an ar-

ray of 28F008SAs for solid-state storage can lower

RP to VIL in standby or sleep modes producing

negligable power consumption If access to the

28F008SA is again needed the part can again be

read following the tPHQV and tPHWL wakeup cycles

required after RP is first raised back to VIH See

AC Characteristics Read-Only and Write Opera-

tions and Figures 10 and 11 for more information

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