NJU6677 データシートの表示（PDF） - Japan Radio Corporation

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NJU6677

88-common x 132-segment BIT MAP LCD DRIVER

Japan Radio Corporation  

NJU6677

(1-8) Reset Circuit

Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level.

Initialization

1 Display Off

2 Normal Display (Non-inverse display)

3 ADC Select : Normal (ADC Instruction D0 =”0”)

4 Read Modify Write Mode Off

5 Internal Power supply (Voltage Booster) circuits Off

6 Static Drive Off

7 Driver Output Off

8 Clear the serial interface register

9 Set the address(00)H to the Column Address Counter

10 Set the 1st Line in the Display Start Line Register.page (00)H to the Page Address Register

11 Set the page “0” to the Page Address Register

12 Set the EVR register to (FF)H

13 Set the All display(1/88 duty)

14 Set the Bias select(1/10 Bias)

15 Set the 5-Time Voltage Booster

16 Set the n line turn over register (0)H

The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time

with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L"

level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation

goes to normal.

When the internal LCD power supply is not used, the external LCD power supply into the NJU6677 must be

turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the

oscillation circuit and the output terminal conditions (D0 to D7) are not influenced. The initialization must be

performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset

Instruction performs the initialization procedures from No.9 to No.16 as shown in above.

Note) The noise into the RES terminal should be eliminated to avoid the error on the application with the

careful design.

(1-9) LCD Driving

(a) LCD Driving Circuits

LCD driving circuits are consisted of 220 multiplexers which operate as 132 Segment drivers and 88 Common

drivers. 88 Common drivers with the shift register scan the common display signal. The combination of the

Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave form

is shown in the Fig. 7.

(b) Display Data Latch Circuits

Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common

cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse

ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display

Data RAM is not changed.

(c) Line Counter and Latch signal of Latch Circuits

The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock

(CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display

data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving

circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by

the MPU.

(d) Display Timing Generator

Display Timing Generator generates the timing signal for the display system by combination of the master

clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate

LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.

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