CY7C4241-10JI データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C4241-10JI Datasheet PDF : 20 Pages
| |||
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms
WCLK
D0 –D8
WEN1
tCLKH
Figure 5. Write Cycle Timing
tCLK
tCLKL
tDS
tDH
tENS
tENH
WEN2
(if applicable)
FF
RCLK
tWFF
tSKEW1[14]
tWFF
NO OPERATION
NO OPERATION
REN1,REN2
RCLK
REN1,REN2
tENS
EF
Q0 –Q8
OE
tOLZ
WCLK
WEN1
tCLKH
Figure 6. Read Cycle Timing
tCKL
tCLKL
tENH
tREF
tA
NO OPERATION
tOE
[15]
tSKEW1
tREF
VALID DATA
tOHZ
WEN2
Notes
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
Document #: 38-06016 Rev. *D
Page 11 of 20
[+] Feedback
Share Link: 