SAA2502 データシートの表示（PDF） - Philips Electronics
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SAA2502 Datasheet PDF : 64 Pages
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Philips Semiconductors
ISO/MPEG Audio Source Decoder
Preliminary specification
SAA2502
7.3.1 MASTER INPUT MODE
Master input mode is the default mode of operation. This
mode may also be enforced by setting the INMOD control
flags to 00. Which means that the SAA2502 will generate
requests for input data at regular intervals. CDVAL is not
used in this mode (it should be connected to VSS or VDD).
CDVAL is implicitly assumed to be logic 1 during the 2nd
up to (and including) the 17th bit slot after a rising or a
falling edge of CDRQ (see Fig.7). Thus signal CD should
carry the coded data in bursts of 16 valid bits.
In this mode the CDRQ frequency is locked to (i.e. derived
from) the 256 × fs clock. Its average value equals the bit
rate divided by 32.
The bit clock CDCL is output, its frequency is fixed:
M------C3----2-L----K-- when MCLK24 = logic 1
M------C1----6-L----K-- when MCLK24 = logic 0.
MPEG free format bit rate is NOT allowed in this mode.
Assume N is the number of CDCL periods between two
transitions of CDRQ, and R is the number of CDCL periods
to obtain the effective bit rate E (in kbits/s) at a CDCL
frequency of 768 kHz, i.e. R = 1----6-----×-E----7---6---8-- .
The SAA2502 keeps the average value of N exactly at R,
but individual values of N may vary between
N = round (R) −2 and N = round (R) +2.
7.3.2 SLAVE INPUT MODE
Slave input mode is activated by setting the INMOD control
flags to 0 1. Which means that the SAA2502 will accept
input data as presented by the application. In this mode it
is the responsibility of the application to maintain locking
between the 256 × fs sample clock and the average bit
rate.
handbook, full pagewidth
CDCL
CD,,,,,,,,1 2
,,,,,,,,,,,, 14
15
16
1
2
CDEF
unreliable data bit (example)
CDRQ
CDSY
start of byte or frame
valid data
valid but unreliable data
MGE474
, invalid data
1997 Nov 17
Fig.7 Master mode input data format.
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