SAA2502 データシートの表示（PDF） - Philips Electronics

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SAA2502

ISO/MPEG Audio Source Decoder

Philips Electronics 

Philips Semiconductors

ISO/MPEG Audio Source Decoder

Preliminary specification

SAA2502

7.3.3 BUFFER CONTROLLED INPUT MODE (see Fig.10)

Buffer controlled input mode is activated by setting the

INMOD control flags to 1X, which means that the SAA2502

will request data based on the amount of input bytes

currently residing in the input buffer.

The bit clock CDCL is output, its frequency is fixed:

M------C3----2-L----K-- when MCLK24 = logic 1

M------C1----6-L----K-- when MCLK24 = logic 0.

In this mode CDRQ = logic 1 is an indication that new input

data is required. CDVAL = logic 1 indicates the delivery of

valid data. The application should react to the event of an

input data request as follows:

• One byte of input data should be delivered within

16 CDCL cycles. If CDRQ remains high the next byte

should be delivered and so on until CDRQ is dropped.

Delivery of subsequent bytes while CDRQ remains

HIGH should be uninterrupted (CDVAL should stay

HIGH)

• There is also an option for the application to deliver part

of the input data later. Despite violating the conditions in

the previous paragraph, this is allowed, but with

consequences for the input buffer latency time.

MPEG free format bit rate is allowed in this mode.

Dynamically varying bit rate may be supported in this

mode. Whether such support is desired or not is indicated

by the following input mode bits:

• INPMOD = 10 means bit rate is assumed to be (quasi)

static

• INPMOD = 11 means bit rate is assumed to be dynamic.

handbook, full pagewidth

CDCL

CD ,,,,,,,,,,,,

CDEF

unreliable data bit (example)

,,,,,,

CDRQ

CDVAL

CDSY

start of byte or frame

valid data

1997 Nov 17

valid but unreliable data

Fig.10 Buffer controlled mode input data format.

15

,,,, MGE477

invalid data

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