SAA7392 データシートの表示（PDF） - Philips Electronics

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SAA7392

Channel encoder/decoder CDR60

Philips Electronics 

Philips Semiconductors

Channel encoder/decoder CDR60

Preliminary specification

SAA7392

7.3 System clocks

The principle clocks used in the SAA7392 are derived from the crystal oscillator input pin XTLI (alternatively, an external

clock can be connected to this pin). These clocks are the system clock (also used as the ADC clock) and the I2S output

bit clock (BCLK).

The system clock (fclk) defines the maximum operational channel rate for the device. The maximum EFM channel clock

is twice the system clock, for CD it is equivalent to system clock/(4.3 × 106) which is approximately 11.5 × CDROM for a

25 MHz system clock.

The other clock in the system is the channel data clock, this is recovered by the front-end bit recovery PLL.

handbook, full pagewidth

MUXSWI

crystal

oscillator

XTLI

XTLO

CL1

×

M × XTLI

CLOCK (1)

MULTIPLIER

XTLI

SYSTEM

CLOCK

DIVIDER

BIT

CLOCK

DIVIDER

system clock

BCLK

CL1

DIVIDER

system clock

MGR795

(1) M = 1 if MUXSWI is LOW; M = 8 if MUXSWI is HIGH.

Fig.5 System clock generator.

2000 Mar 21

16

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