SAA7392 データシートの表示（PDF） - Philips Electronics

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SAA7392

Channel encoder/decoder CDR60

Philips Electronics 

Philips Semiconductors

Channel encoder/decoder CDR60

Preliminary specification

SAA7392

7.5.1 DIGITAL PLL

The digital PLL will recover the channel bit clock. As the

capture range of the PLL itself is limited, lock detectors and

2 capture aids are present. In total three different PLL

operation modes exist: In-lock, Inner-lock aid and

Outer-lock aid.

The PLL behaviour during in-lock (the normal on-track

situation) can be best explained in the frequency domain.

The PLL operation is completely linear during in-lock

situations. The open-loop response of the PLL is given in

Fig.7. The three frequencies, f0 (integrator cross-over

frequency), f1 (PLL bandwidth) and f2 (low-pass

bandwidth) are programmable via register PLLSet.

To extend the PLL capture range two lock aids are used:

• Inner lock aid: has a capture range of ±10% and will

bring the PLL frequency to the lock point

• Outer lock range: has no limitation on capture range,

and will bring the PLL within the range of the inner lock

range.

Two outer lock aids can be used:

• Run length 3 deviation detector: this circuit is known to

be sensitive to systematic over/under equalization; this

over/under equalization can be counter-acted by writing

a non-zero phase offset value to register PLLLock.

• Frequency measurement detector: this circuit regulates

the PLL frequency so that the average number of EFM

transitions is a fixed fraction of the PLL bit clock; the

transition frequency is settable via register PLLFMeas.

Programmability/observability is built into the PLL. Its

operation can be influenced in two ways:

• It is possible to select the state the PLL is in (in-lock,

near-lock, outer-lock) via register PLLLock

• It is possible to preset the PLL frequency to a certain

value via registers PLLEqu and PLLFreq.

The operation of the bit detector can be monitored by the

microprocessor and via the MEAS1 pin. Four signals are

available for measurement:

• PLL frequency signal: the most significant 8 bits are

available via register PLLLock

• Asymmetry signal: the 8-bit signal in 2’s complement

form is available via register PLLSet

• Jitter signal: the most significant 8 bits are available via

register PLLFreq. This gives an impression of the

detection jitter after all processing is done.

jitter<9:0> = average ((jitter individual

transition)2 × 8192)

To obtain the jitter in the bit clocks the jitter<9:0> value

must be divided by 8192 and square routed. Note that

the jitter<9:0> overestimates the jitter (by approximately

rms jitter increase of 0.03 bit clock), because the

quantization of the zero transitions is in 4 intervals.

Note the jitter is measured before the bit detection and

contains contributions due to various imperfections in

the complete signal path; i.e. disc, preamplifier, ADC,

limited bitwidths, PLL performance, internal filter noise,

asymmetry compensation, equalizer.

• Internal lock flags: The internally generated inner-lock

signal (f_lock_in), lock signal (lock_in) and flag that

indicates when a run length 14 is detected

(long_symbol) are available via register PLLEqu.

handbook, halfpage

amplitude

(dB)

f0 f1

f2

frequency (Hz)

MGR797

Fig.7 PLL bode diagram.

2000 Mar 21

20

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