SCC2698B データシートの表示（PDF） - Philips Electronics
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SCC2698B Datasheet PDF : 29 Pages
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Philips Semiconductors
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Product specification
SCC2698B
Table 2. Register Bit Formats (Continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSR (Clock Select Register)
Receiver Clock Select
See text
Transmitter Clock Select
See text
* See Table 5 for BRG Test frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68681 and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
OPCR (Output Port Configuration Register) This register controls the MPP I/O pins and the MPO multi-purpose output pins.
MPP Function
Select
MPOb Pin Function Select
Power-Down
Mode*
MPOa Pin Function Select
0 = input
000 = RTSN
0 = Off
000 = RTSN
1 = output
001 = C/TO
1 = On
001 = C/TO
010 = TxC (1X)
010 = TxC (1X)
011 = TxC (16X)
011 = TxC (16X)
100 = RxC (1X)
100 = RxC (1X)
101 = RxC (16X)
101 = RxC (16X)
110 = TxRDY
110 = TxRDY
111 = RxRDY/FF
111 = RxRDY/FF
NOTE: *Only OPCR[3] in block A controls the power-down mode.
ACR (Auxiliary Control Register)
BRG Select
Counter/Timer Mode and Source
0 = set 1
1 = set 2
See Text
Delta
MPI1bINT
0 = off
1 = on
Delta
MPI0bINT
0 = off
1 = on
Delta
MPI1aINT
0 = off
1 = on
Delta
MPI0aINT
0 = off
1 = on
IPCR (Input Port Change Register)
Delta MPI1b Delta MPI0b Delta MPI1a
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
Delta MPI0a
0 = No
1 = Yes
MPI1b
0 = Low
1 = High
MPI0b
0 = Low
1 = High
MPI1a
0 = Low
1 = High
MPI0a
0 = Low
1 = High
ISR (Interrupt Status Register)
MPI Port
Change
Delta BREAKb
0 = No
1 = Yes
0 = No
1 = Yes
RxRDY/
FFULLb
0 = No
1 = Yes
TxRDYb
0 = No
1 = Yes
Counter
Ready
0 = No
1 = Yes
Delta BREAKa
0 = No
1 = Yes
RxRDY/
FFULLa
0 = No
1 = Yes
TxRDYa
0 = No
1 = Yes
IMR (Interrupt Mask Register)
MPI Port Delta BREAKb
Change INT
INT
0 = off
1 = on
0 = off
1 = on
RxRDY/
FFULLb INT
0 = off
1 = on
TxRDYb INT
0 = off
1 = on
Counter
Ready INT
0 = off
1 = on
Delta BREAKa
INT
0 = off
1 = on
RxRDY/
FFULLa INT
0 = off
1 = on
TxRDYa INT
0 = off
1 = on
CTPU (Counter/Timer Upper Register)
C/T[15]
C/T[14]
C/T[13]
C/T[12]
C/T[11]
C/T[10]
C/T[9]
C/T[8]
CTPU (Counter/Timer Lower Register)
C/T[7]
C/T[6]
C/T[5]
C/T[4]
C/T[3]
C/T[2]
C/T[1]
C/T[0]
IPR (Input Port Register) MPP and MPI Pins
MPP2b
MPP1b
MPP2a
MPP1a
MPI1b
MPI0b
MPI1a
MPI0a
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
NOTE: When TxEMT and TxRDY bits are at one just before a write to the Transmit Holding register, a command to disable the transmitter
should be delayed until the TxRDY is at one again. TxRDY will set to one at the end of the start bit time.
2000 Jan 31
14
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