SCC2698B データシートの表示（PDF） - Philips Electronics
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SCC2698B Datasheet PDF : 29 Pages
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Philips Semiconductors
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Product specification
SCC2698B
DC ELECTRICAL CHARACTERISTICS1, 2, 3 TA = 0 to +70_, VCC = 5.0 V " 10%, –40 to 85_C
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min
Typ
Max
UNIT
VIL
Input low voltage
VIH
Input high voltage (except X1/CLK)
VIH
Input high voltage (X1/CLK)
2.0
0.8VCC
0.8
V
V
V
VOL
Output Low voltage
VOH
Output High voltage (except OD outputs)
IIL
Input current Low, MPI and MPP pins
IIH
Input current High, MPI and MPP pins
II
Input leakage current
IOL = 2.4mA
IOH = –400µA
IOH = –100µA
VIN = 0
VIN = VCC
VIN = 0 to VCC
0.8VCC
0.9VCC
–50
–10
0.4
V
V
V
20
µA
µA
10
µA
IILX1
IIHX1
IOZH
IOZL
IODL
IODH
ICC
X1/CLK input Low current
X1/CLK input High current
Output off current High, 3-State data bus
Output off current Low, 3-State data bus
Open-drain output Low current in off state: IRQN
Open-drain output Low current in off state: IRQN
Power supply current
Operating mode
Power down mode9
VIN = GND, X2 = open
VIN = VCC, X2 = open
VIN = VCC
VIN = 0
VIN = VCC
VIN = 0
–100
–10
–10
µA
100
µA
10
µA
10
µA
30
mA
2.0
mA
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of VIL and VIH, as
appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for interrupt and MPP outputs: CL = 50pF, RL = 2.7kΩ to VCC. Test conditions for rest of outputs: CL = 150pF.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for tRWD guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three edges of the X1 clock between writes.
8. This value is not tested, but is guaranteed by design.
9. See UART applications note for power down currents less than 5µA.
10. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
11. Address is latched on leading edge of read or write cycle.
2000 Jan 31
19
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