SCC2698B データシートの表示（PDF） - Philips Electronics
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SCC2698B Datasheet PDF : 29 Pages
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Philips Semiconductors
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
Product specification
SCC2698B
0101
0110
0111
1000
1001
1010
1011
1100
1101
111x
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2 or 6]) to
be cleared to zero.
Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will
be delayed up to two bit times. If the transmitter is active,
the break begins when transmission of the character is
completed. If a character is in the THR, the start of break
is delayed until that character or any others loaded after
it have been transmitted (TxEMT must be true before
break begins). The transmitter must be enabled to start a
break
Stop break. The TxD line will go high (marking) within
two bit times. TxD will remain high for one bit time before
the next character, if any, is transmitted.
Assert RTSN. Causes the RTSN output to be asserted
(Low).
Negate RTSN. Causes the RTSN output to be negated
(High).
Set Timeout Mode On. The register in this channel will
restart the C/T as each receive character is transferred
from the shift register to the RHR. The C/T is placed in
the counter mode, the START/STOP counter commands
are disabled, the counter is stopped, and the Counter
Ready Bit, ISR[3], is reset.
Reserved.
Disable Timeout Mode. This command returns control of
the C/T to the regular START/STOP counter commands.
It does not stop the counter, or clear any pending
interrupts. After disabling the timeout mode, a ‘Stop
Counter’ command should be issued.
Reserved.
Reserved for testing.
CR[3] – Disable Transmitter
This command terminates transmitter operation and resets the
TxRDY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the THR when the transmitter is
disabled, the transmission of the character(s) is completed before
assuming the inactive state.
CR[2] – Enable Transmitter
Enables operation of the transmitter. The TxRDY status bit will be
asserted.
CR[1] – Disable Receiver
This command terminates operation of the receiver immediately – a
character being received will be lost. The command has no effect on
the receiver status bits or any other control registers. If the special
wake–up mode is programmed, the receiver operates even if it is
disabled (see Wake-up Mode).
CR[0] – Enable Receiver
Enables operation of the receiver. If not in the special wake-up
mode, this also forces the receiver into the search for start bit state.
SR – Channel Status Register
SR[7] – Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxDA line returns to the marking state
for at least one-half bit time two successive edges of the internal or
external 1x clock. This will usually require a high time of one X1
clock period or 3 X1 edges since the clock of the controller is
not synchronous to the X1 clock.
When this bit is set, the change in break bit in the ISR (ISR[6 or 2])
is set. ISR[6 or 2] is also set when the end of the break condition, as
defined above, is detected. The break detect circuitry is capable of
detecting breaks that originate in the middle of a received character.
However, if a break begins in the middle of a character, it must last
until the end of the next character in order for it to be detected.
SR[6] – Framing Error (FE)
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SR[5]– Parity Error (PE)
This bit is set when the ‘with parity’ or ‘force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In special ‘wake-up mode’, the parity
error bit stores the received A/D bit.
SR[4] – Overrun Error (OE)
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the FIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost. This bit is
cleared by a reset error status command.
SR[3] – Transmitter Empty (TxEMT)
This bit will be set when the transmitter underruns, i.e., both the
transmit holding register and the transmit shift register are empty. It
is set after transmission of the last stop bit of a character, If no
character is in the THR awaiting transmission. It is reset when the
THR is loaded by the CPU, or when the transmitter is disabled.
SR[2] – Transmitter Ready (TxRDY)
This bit, when set, indicates that the THR is empty and ready to be
loaded with a character. This bit is cleared when the THR is loaded
by the CPU and is set when the character is transferred to the
transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
characters loaded in the THR while the transmitter is disabled will
not be transmitted.
SR[1] – FIFO Full (FFULL)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all three FIFO positions are occupied. It is reset
when the CPU reads the FIFO and there is no character in the
receive shift register. If a character is waiting in the receive shift
register because the FIFO is full, FFULL is not reset after reading
the FIFO once.
SR[0] – Receiver Ready (RxRDY)
This bit indicates that a character has been received and is waiting
in the FIFO to be read by the CPU. It is set when the character is
transferred from the receive shift register to the FIFO and reset
when the CPU reads the RHR, and no more characters are in the
FIFO.
2000 Jan 31
16
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