SI3233 データシートの表示（PDF） - Silicon Laboratories

部品番号

コンポーネント説明

メーカー

SI3233

PROSLIC® PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION

Silicon Laboratories 

Si3233

Table 9. Switching Characteristics—General Inputs

VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade, CL = 20 pF)

Parameter

Symbol

Min

Typ

Max

Unit

Rise Time, RESET

tr

—

—

20

ns

RESET Pulse Width

trl

100

—

—

ns

Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are

VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.

Table 10. Switching Characteristics—SPI

VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70°C for F-Grade, –40 to 85°C for G-Grade, CL = 20 pF

Parameter

Symbol

Test

Conditions

Min

Typ

Max

Unit

Cycle Time SCLK

tc

0.062

—

—

µs

Rise Time, SCLK

tr

—

—

25

ns

Fall Time, SCLK

tf

—

—

25

ns

Delay Time, SCLK Fall to SDO Active

td1

—

—

20

ns

Delay Time, SCLK Fall to SDO

td2

Transition

—

—

20

ns

Delay Time, CS Rise to SDO Tri-state

td3

—

—

20

ns

Setup Time, CS to SCLK Fall

tsu1

25

—

—

ns

Hold Time, CS to SCLK Rise

th1

20

—

—

ns

Setup Time, SDI to SCLK Rise

tsu2

25

—

—

ns

Hold Time, SDI to SCLK Rise

th2

20

—

—

ns

Delay Time between Chip Selects

tcs

(Continuous SCLK)

440

—

—

ns

Delay Time between Chip Selects

tcs

(Non-continuous SCLK)

220

—

—

ns

SDI to SDITHRU Propagation Delay

td4

—

4

10

ns

Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V

10

Preliminary Rev. 0.5

Share Link: