87C196(1998) データシートの表示（PDF） - Intel
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87C196 Datasheet PDF : 38 Pages
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87C196CA/87C196CB - Express
5.1.1
5.1.1.1
5.1.1.2
8xC196CB Additional Bus Timing Modes
The 8xC196CB device has two bus timing modes for external memory interfacing.
MODE 3
Mode 3 is the standard timing mode. Use this mode for systems that emulate the 8xC196KR bus
timings.
MODE 0
Mode 0 is the standard timing mode, but 1 (minimum) wait state is always inserted in external bus
cycles.
5.2
AC CHARACTERISTICS
5.2.1
Test Conditions
• Capacitive load on all pins = 100 pF
• Rise and Fall Times = 10 ns
Table 6. AC Characteristics the 87C196CA/87C196CB - Express Meets (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Units
FXTAL
Frequency on XTAL1
4
16
MHz (1)
TOSC
XTAL1 Period (1/FXTAL)
62.5
250
ns
TXHCH
XTAL1 High to CLKOUT High or Low
+ 20
110
ns
TOFD
Clock Failure to Reset Pulled Low
4
40
µs (6)
TCLCL
CLKOUT Period
2TOSC
ns
TCHCL
CLKOUT High Period
TOSC–10
TOSC+15
ns
TCLLH
CLKOUT Low to ALE/ADV High
–15
+ 10
ns
TLLCH
ALE/ADV# Lowe to CLKOUT High
–20
+ 15
ns
TLHLH
ALE/ADV# Cycle Time
4TOSC
ns (5)
TLHLL
ALE/ADV# High Time
TOSC–10
TOSC+10
ns
TAVLL
Address Valid to ALE Low
TOSC–15
ns
TLLAX
Address Hold after ALE/ADV# Low
TOSC–40
ns
TLLRL
ALE/ADV# Low to RD# Low
TOSC–30
ns
NOTES:
1. Testing performed at 4 MHz, however, the device is static by design and typically operates below 1 Hz.
2. Typical specifications, not guaranteed.
3. Assuming back-to-back bus cycles.
4. 8-bit bus only.
5. If wait states are used, add 2TOSC x n = number of wait states. If mode 0 (1 automatic wait state added)
operation is selected, add 2TOSC to specification.
6. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is
enabled by programming the UPROM location 0778H with the value 0004H. Programming the CDE bit
enables oscillator fail detection.
14
ADVANCE INFORMATION Datasheet
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