SST36VF1601 データシートの表示（PDF） - Silicon Storage Technology
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SST36VF1601 Datasheet PDF : 26 Pages
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16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
1
Temperature Under Bias ................................................................................................................... -55°C to +125°C
2
Storage Temperature ........................................................................................................................ -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VDD + 1.0V
3
Package Power Dissipation Capability (Ta = 25°C) ............................................................................................ 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) .................................................................................. 240°C
4
Output Short Circuit Current ............................................................................................................................. 50 mA
5
OPERATING RANGE
AC CONDITIONS OF TEST
Range
Ambient Temp
Commercial 0 °C to +70 °C
VDD
2.7-3.6V
Input Rise/Fall Time ......... 5 ns
Output Load ..................... CL = 30 pF
6
Extended
-20 °C to +85 °C
2.7-3.6V
See Figures 16 and 17
7
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
8
Limits
Symbol Parameter
Min Max Units Test Conditions
IDD
Power Supply Current
Read
Program and Erase
Concurrent
ISB
Standby VDD Current
CE#=OE#=VIL,WE#=VIH , all I/Os open,
9
35
mA Address input = VIL/VIH, at f=1/TRC Min.
40
mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max.
75
mA
10
20
µA
CE#=VIHC, VDD = VDD Max.
IALP
Auto Low Power Current
20
µA
CE#=VILC, VDD = VDD Max., all inputs =
VIHC or VILC, WE# = VIHC
11
IRT
Reset VDD Current
20
µA RESET# = VSS ± 0.3V
ILI
Input Leakage Current
ILO
Output Leakage Current
1
µA
VIN =GND to VDD, VDD = VDD Max.
1
µA
VOUT =GND to VDD, VDD = VDD Max.
12
VIL
Input Low Voltage
0.8
V
VDD = VDD Min.
VILC
Input Low Voltage (CMOS)
0.3
V
VDD = VDD Max.
13
VIH
Input High Voltage
0.7 VDD
V
VDD = VDD Max.
VIHC
Input High Voltage (CMOS) VDD-0.3
V
VDD = VDD Max.
VOL
Output Low Voltage
0.2
V
IOL = 100 µA, VDD = VDD Min.
14
VOH
Output High Voltage
VDD-0.2
V
IOH = -100 µA, VDD = VDD Min.
373 PGM T8.2
15
16
© 2000 Silicon Storage Technology, Inc.
11
S71142
373-3 11/00
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