SST49LF004B PDF VIEW DOWNLOAD, SST49LF004B データシート

SST49LF004B データシートの表示（PDF） - Silicon Storage Technology

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SST49LF004B

4 Mbit Firmware Hub

Silicon Storage Technology

SST49LF004B Datasheet PDF : 36 Pages

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EOL Data Sheet

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles after

the start of a bus cycle, the cycle will be terminated. The

host may drive LAD[3:0] with '1111b' (ABORT nibble) to

return the interface to ready mode. The ABORT only

affects the current bus cycle. For a multi-cycle command

sequence, such as the Erase or Program SDP commands,

ABORT doesn't interrupt the entire command sequence,

only the current bus cycle of the command sequence. The

host can re-send the bus cycle for the aborted command

and continue the SDP command sequence after the device

is ready again.

Response to Invalid Fields for Firmware

Memory Cycle

During LPC operations the SST49LF004B will not explicitly

indicate that it has received invalid field sequences. The

response to specific invalid fields or sequences is as fol-

lows:

ID mismatch: If the IDSEL field does not match ID[3:0],

the device will ignore the cycle. See Multiple Device Selec-

tion section for details.

Address out of range: The address sequence is 7

fields long (28 bits) for Firmware Memory bus cycles, but

only A22 and A18:A0 will be decoded by SST49LF004B.

Address A22 has the special function of directing reads and

writes to the flash core (A22=1) or to the register space

(A22=0).

Invalid MSIZE field If the device receives an invalid

MSIZE field during a Firmware Memory Read or Write

cycle, the cycle will be ignored and no operation will be

attempted. The SST49LF004B will not generate any kind

of response in this situation. Invalid size fields for a Firm-

ware Memory cycle are any data other than 0000b.

Once valid START, IDSEL, and MSIZE fields are received,

the SST49LF004B will always complete the bus cycle.

However, if the device is busy performing a flash Erase or

Program operation, no new Write command (memory write

or register write) will be executed.

4 Mbit Firmware Hub

SST49LF004B

Multiple Device Selection

Multiple LPC flash devices may be strapped to increase

memory densities in a system. The four ID pins, ID[3:0],

allow up to 16 devices to be attached to the same bus by

using different ID strapping in a system. BIOS support, bus

loading, or the attaching bridge may limit this number. The

boot device must have an ID of 0000b (determined by

ID[3:0]); subsequent devices use incremental numbering.

Equal density must be used with multiple devices.

Multiple Device Selection for

Firmware Memory Cycle

For Firmware Memory Read/Write cycles, hardware strap-

ping values on ID[3:0] must match the values in IDSEL

field. See Table 6 for multiple device selection configura-

tions. The SST49LF004B will compare the IDSEL field with

ID[3:0]'s strapping values. If there is a mismatch, the device

will ignore the reminder of the cycle.

TABLE 6: FIRMWARE MEMORY MULTIPLE DEVICE

SELECTION CONFIGURATION

Device #

0 (Boot device)

ID[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

IDSEL