SST49LF040 データシートの表示（PDF） - Silicon Storage Technology
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SST49LF040 Datasheet PDF : 48 Pages
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4 Mbit LPC Flash
SST49LF040
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this
datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Commercial
Ambient Temp
0°C to +85°C
VDD
3.0-3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 29 and 30
TABLE 9: DC OPERATING CHARACTERISTICS (ALL INTERFACE)
Symbol Parameter
IDD
Active VDD Current
Limits
Min
Max
Read
12
Write2
24
ISB
Standby VDD Current
100
(LPC Interface)
IRY3
Ready Mode VDD Current (LPC Interface)
10
II
Input Current for IC:
ID[3:0] pins for SST49LF040
ID[3:1] pins for SST49LF080A
ILI
Input Leakage Current
ILO
Output Leakage Current
VIHI
INIT# Input High Voltage
VILI
INIT# Input Low Voltage
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
200
1.1
-0.5
-0.5
0.5 VDD
0.9 VDD
1
1
VDD+0.5
0.4
0.3 VDD
VDD+0.5
0.1 VDD
1. Test conditions apply to PP mode.
2. IDD active while Erase or Program is in progress.
3. The device is in Ready Mode when no activity is on the LPC bus.
Units
mA
mA
µA
mA
µA
µA
µA
V
V
V
V
V
V
Test Conditions1
Address input=VIL/VIH, at f=1/TRC Min,
VDD=VDD Max
OE#=VIL, WE#=VIH, All I/Os open
OE#=VIH, VDD=VDD Max
LFRAME#=VIH, f=33 MHz, CE#=VIH
VDD=VDD Max,
All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
LFRAME#=VIL, f=33 MHz, VDD=VDD Max
All other inputs ≥ 0.9 VDD or ≤ 0.1 VDD
VIN=GND to VDD, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Max
VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
IOL=1500µA, VDD=VDD Min
IOH=-500 µA, VDD=VDD Min
T9.1 562
©2001 Silicon Storage Technology, Inc.
17
S71213-00-000 11/01 562
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