SST49LF040 データシートの表示（PDF） - Silicon Storage Technology

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SST49LF040

4 Mbit LPC Flash

Silicon Storage Technology 

4 Mbit LPC Flash

SST49LF040

Advance Information

TABLE 14: RESET TIMING PARAMETERS (LPC MODE), VDD=3.0-3.6V

Symbol Parameter

Min

TPRST

TKRST

TRSTP

TRSTF

TRST1

TRSTE

VDD stable to Reset Low

1

Clock Stable to Reset Low

100

RST# Pulse Width

100

RST# Low to Output Float

RST# High to LFRAME# Low

1

RST# Low to reset during Sector-/Block-Erase or Program

Max

48

10

1. There will be a latency of TRSTE if a reset procedure is performed during a programming or erase operation,

Units

ms

µs

ns

ns

µs

µs

T14.0 562

VDD

CLK

RST#/INIT#

LAD[3:0]

LFRAME#

TPRST

TKRST

FIGURE 7: RESET TIMING DIAGRAM

TRSTP

TRSTF

TRSTE

TRST

Sector-/Block-Erase

or Program operation

aborted

562 ILL F06.0

©2001 Silicon Storage Technology, Inc.

19

S71213-00-000 11/01 562

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