T431616B データシートの表示（PDF） - Taiwan Memory Technology

部品番号

コンポーネント説明

メーカー

T431616B

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616B

Page Read & Write Cycle at Same Bank @ Burst Length = 4

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

HIGH

CS

RAS

CAS

tR C D

t CCD

*Note2

ADDR

Ra

Ca0

Cb0

Cc0

Cd0

BA

A10/AP

CL=2

DQ

CL=3

Qa0 Qa1 Qb0 Qb1 Qb2

Qa0 Qa1 Qb0 Qb1

tR D L

Dc0 Dc1 Dd0 Dd1

tC D L

Dc0 Dc1 Dd0 Dd2

WE

DQM

*Note1

*Note3

Row Active

(A-Bnak)

Read (A-

Bnak)

Read (A-

Bnak)

Write (A-

Bnak)

Write (A-

Bnak)

Precharge

(A-Bnak)

:Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to

avoid bus contention.

2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge before

end of burst. Input data after Row precharge cycle will be masked internally.

Taiwan Memory Technology, Inc. reserves the right P.18

to change products or specifications without notice.

Publication Date: JUL. 2001

Revision:A

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