M80C186 データシートの表示（PDF） - Intel

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M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

M80C186

dress to an odd address This is a total of 16 clocks

or more if WAIT states are required In addition if

locked transfers are performed the HOLD latency

time will be increased by the length of the locked

transfer

Local Bus Controller and Reset

Upon receipt of a RESET pulse from the RES input

the local bus controller will perform the following ac-

tion

 Drive DEN RD and WR HIGH for one clock cy-

cle then float

NOTE

RD is also provided with an internal pull-up device

to prevent the processor from inadvertently enter-

ing Queue Status mode during reset

 Drive S0–S2 to the passive state (all HIGH) and

then float

 Drive LOCK HIGH and then float

 Float AD0–15 A16–19 BHE DT R

 Drive ALE LOW (ALE is never floated)

 Drive HLDA LOW

INTERNAL PERIPHERAL INTERFACE

All the M80C186 integrated peripherals are con-

trolled via 16-bit registers contained within an inter-

nal 256-byte control block This control block may

be mapped into either memory or I O space Internal

logic will recognize the address and respond to the

bus cycle During bus cycles to internal registers the

bus controller will signal the operation externally

(i e the RD WR status address data etc lines

will be driven as in a normal bus cycle) but D15–0

SRDY and ARDY will be ignored The base address

of the control block must be on an even 256-byte

boundary (i e the lower 8 bits of the base address

are all zeros) All of the defined registers within this

control block may be read or written by the

M80C186 CPU at any time The location of any reg-

ister contained within the 256-byte control block is

determined by the current base address of the con-

trol block

The control block base address is programmed via a

16-bit relocation register contained within the control

block at offset FEH from the base address of the

control block (see Figure 9) It provides the upper 12

bits of the base address of the control block The

control block is effectively an internal chip select

range and must abide by all the rules concerning

chip selects (the chip select circuitry is discussed

later in this data sheet) Any access to the 256 bytes

of the control block activates an internal chip select

Other chip selects may overlap the control block

only if they are programmed to zero wait states and

ignore external ready In addition bit 12 of this regis-

ter determines whether the control block will be

mapped into I O or memory space If this bit is 1 the

control block will be located in memory space

whereas if the bit is 0 the control block will be locat-

ed in I O space If the control register block is

mapped into I O space the upper 4 bits of the base

address must be programmed as 0 (since I O ad-

dresses are only 16 bits wide)

In addition to providing relocation information for the

control block the relocation register contains bits

which place the interrupt controller into slave mode

and cause the CPU to interrupt upon encountering

ESC instructions At RESET the relocation register

is set to 20FFH This causes the control block to

start at FF00H in I O space An offset map of the

256-byte control register block is shown in Figure

10

The integrated M80C186 peripherals operate semi-

autonomously from the CPU Access to them for the

most part is via software read write of the control

block Most of these registers can be both read and

written A few dedicated lines such as interrupts and

DMA request provide real-time communication be-

tween the CPU and peripherals as in a more con-

ventional system utilizing discrete peripheral blocks

The overall interaction and function of the peripheral

blocks has not substantially changed

CHIP-SELECT READY GENERATION

LOGIC

The M80C186 contains logic which provides

programmable chip-select generation for both

memories and peripherals In addition it can be pro-

grammed to provide READY (or WAIT state) genera-

tion It can also povide latched address bits A1 and

A2 The chip-select lines are active for all memory

and I O cycles in their programmed areas whether

they be generated by the CPU or by the integrated

DMA unit

Memory Chip Selects

The M80C186 provides 6 memory chip select out-

puts for 3 address areas upper memory lower

memory and midrange memory One each is provid-

ed for upper memory and lower memory while four

are provided for midrange memory

The range for each chip select is user-programma-

ble and can be set to 2K 4K 8K 16K 32K 64K

128K (plus 1K and 256K for upper and lower chip

selects) In addition the beginning or base address

20

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