M80C186 データシートの表示（PDF） - Intel

部品番号

コンポーネント説明

メーカー

M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

M80C186

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET A8H 1 M6 M5 M4 M3 M2 M1 M0 EX MS 1 1 1 R2 R1 R0

Figure 13 MPCS Register

15

9

3

0

OFFSET A6H U U U U U U U 1 1 1 1 1 1 R2 R1 R0

A19

A13

Figure 14 MMCS Register

MMCS bits R2– R0 specify READY mode of opera-

tion for all mid-range chip selects All devices in mid-

range memory must use the same number of WAIT

states

The 512K block size for the mid-range memory chip

selects is a special case When using 512K the

base address would have to be at either locations

00000H or 80000H If it were to be programmed at

00000H when the LCS line was programmed there

would be an internal conflict between the LCS ready

generation logic and the MCS ready generation log-

ic Likewise if the base address were programmed

at 80000H there would be a conflict with the UCS

ready generation logic Since the LCS chip-select

line does not become active until programmed while

the UCS line is active at reset the memory base can

be set only at 00000H If this base address is select-

ed however the LCS range must not be pro-

grammed

Peripheral Chip Selects

The M80C186 can generate chip selects for up to

seven peripheral devices These chip selects are ac-

tive for seven contiguous blocks of 128 bytes above

a programmable base address This base address

may be located in either memory or I O space

Seven CS lines called PCS0 –6 are generated by the

M80C186 The base address is user-programmable

however it can only be a multiple of 1K bytes i e

the least significant 10 bits of the starting address

are always 0

PCS5 and PCS6 can also be programmed to provide

latched address bits A1 A2 If so programmed they

cannot be used as peripheral selects These outputs

can be connected directly to the A0 A1 pins used

for selecting internal registers of 8-bit peripheral

chips This scheme simplifies the hardware interface

because the 8-bit registers of peripherals are simply

treated as 16-bit registers located on even bounda-

ries in I O space or memory space where only the

lower 8-bits of the register are significant the upper

8-bits are ‘‘don’t cares ’’

The starting address of the peripheral chip-select

block is defined by the PACS register (see Figure

15) This register is located at offset A4H in the inter-

nal control block Bits 15 – 6 of this register corre-

spond to bits 19 – 10 of the 20-bit Programmable

Base Address (PBA) of the peripheral chip-select

block Bits 9 – 0 of the PBA of the peripheral chip-se-

lect block are all zeros If the chip-select block is

located in I O space bits 12 – 15 must be pro-

grammed zero since the I O address is only 16 bits

wide Table 10 shows the address range of each

peripheral chip select with respect to the PBA con-

tained in PACS register

15

65

3

0

OFFSET A4H U U U U U U U U U U 1 1 1 R2 R1 R0

A19

A10

Figure 15 PACS Register

23

Share Link: