M80C186 データシートの表示（PDF） - Intel

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M80C186

CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR

Intel 

M80C186

DMA CHANNELS

The M80C186 DMA controller provides two indepen-

dent high-speed DMA channels Data transfers can

occur between memory and I O spaces (e g Mem-

ory to I O) or within the same space (e g Memory

to Memory or I O to I O) Data can be transferred

either in bytes (8 bits) or in words (16 bits) to or from

even or odd addresses Each DMA channel main-

tains both a 20-bit source and destination pointer

which can be optionally incremented or decrement-

ed after each data transfer (by one or two depending

on byte or word transfers) Each data transfer con-

sumes 2 bus cycles (a minimum of 8 clocks) one

cycle to fetch data and the other to store data

DMA Operation

Each channel has six registers in the control block

which define each channel’s specific operation The

control registers consist of a 20-bit Source pointer (2

words) a 20-bit destination pointer (2 words) a 16-

bit Transfer Counter and a 16-bit Control Word The

format of the DMA Control Blocks is shown in Table

13 The Transfer Count Register (TC) specifies the

number of DMA transfers to be performed Up to

64K byte or word transfers can be performed with

automatic termination The Control Word defines the

channel’s operation (see Figure 17) All registers

may be modified or altered during any DMA activity

Any changes made to these registers will be reflect-

ed immediately in DMA operation

Table 13 DMA Control Block Format

Register Name

Register Address

Ch 0

Ch 1

Control Word

Transfer Count

Destination Pointer (upper 4

bits)

Destination Pointer

Source Pointer (upper 4 bits)

Source Pointer

CAH

C8H

C6H

C4H

C2H

C0H

DAH

D8H

D6H

D4H

D2H

D0H

Figure 16 DMA Unit Block Diagram

270500 – 9

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