TFRA08C13 データシートの表示（PDF） - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

Pin Information (continued)

Table 2. Pin Descriptions (continued)

Pins

Symbol Type*

Description

AE9

SECOND

O Second Pulse. A one second timer with an active-high pulse. The

duration of the pulse is one RLCK cycle. Framer_1’s receive line clock

signal (RLCK1) is the default clock source for the internal second pulse

timer. The internal second pulse is retimed in the individual framer sec-

tions with their corresponding receive line clock signal RLCK. When

LORLCK_(N) is active, then Framer_(N + 1)’s receive line clock signal

is used as the clock signal source for the internal second pulse timer.

The second pulse is used for performance monitoring.

D18

CHICK

I CHI Clock. 2.048 MHz,

4.096 MHz, or 8.192 MHz.

A19

CHIFS

I CHI Frame Sync. CHI 8 kHz input frame synchronization pulse. Pulse

width must be a minimum of one clock period of CHICK and a maxi-

mum of a 50% duty cycle square wave.

H24

CHICK-EPLL O Error Phase-Lock Loop Signal. The error signal proportional to the

phase difference between DIV-CHICK and DIV-RLCK as detected from

the internal PLL circuitry (see Table 66. Global Control Register

(GREG8) (008)

G25

DIV-PLLCK

O Divided-Down PLLCK Clock. 32 kHz or 8 kHz clock signal derived

from the PLLCK input signal (see Table 150. CHI Common Control

Register (FRM_PR45) (Y8D)).

G26

PLLCK-EPLL O Error Phase-Lock Loop Signal. The error signal proportional to the

phase difference between DIV-PLLCK and DIV-CHICK as detected by

the internal PLL circuitry (refer to the Phase-Lock Loop section).

H23

DIV-RLCK

O Divided-Down Receive Line Clock. 8 kHz clock signal derived from

the recovered receive line interface unit clock or the RLCK input signal.

The choice of which receive framer clock to use is defined in Table 66.

Global Control Register (GREG8) (008).

H26, J24

J4

V1

DIV-CHICK

DS1/CEPT[1]

DS1/CEPT[2]

O Divided-Down CHI Clock. 8 kHz clock signal derived from the transmit

CHI CLOCK input signal (see Table 66. Global Control Register

(GREG8) (008)).

Iu DS1/CEPT. Strap to VDD to enable DS1 operation in the framer unit.

Strap to VSS to enable CEPT operation in the framer unit.

AE5

DS1/CEPT[3]

AD19

DS1/CEPT[4]

AC20

DS1/CEPT[5]

T25

DS1/CEPT[6]

F26

DS1/CEPT[7]

B12

DS1/CEPT[8]

* Iu indicates an internal pull-up, Id indicates an internal pull-down.

† After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin.

‡ Asserting this pin low will initially force RDY to a low state.

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