8XL196NP データシートの表示（PDF） - Intel

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8XL196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Table 6. Signal Descriptions (Continued)

Name

EA#

EPA3:0

EPORT.3:0

EXTINT0

EXTINT1

EXTINT2

EXTINT3

HLDA#

Type

Description

I

External Access

This input determines whether memory accesses to special-purpose and program

memory partitions (FF2000–FF2FFFH) are directed to internal or external memory.

These accesses are directed to internal memory if EA# is held high and to external

memory if EA# is held low. For an access to any other memory location, the value

of EA# is irrelevant.

EA# is not latched and can be switched dynamically during normal operating mode.

Be sure to thoroughly consider the issues, such as different access times for

internal and external memory, before using this dynamic switching capability.

Always connect EA# to VSS when using a microcontroller that has no internal

nonvolatile memory.

I/O Event Processor Array (EPA) Capture/Compare Channels

High-speed input/output signals for the EPA capture/compare channels.

EPA3:0 share package pins with P1.3:0.

I/O Extended Addressing Port

This is a 4-bit, bidirectional, memory-mapped port.

EPORT.3:0 share package pins with A.19:16.

I External Interrupts

In normal operating mode, a rising edge on EXTINTx sets the EXTINTx interrupt

pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The minimum

high time is one state time.

In standby and powerdown modes, asserting the EXTINTx signal for at least 50 ns

causes the device to resume normal operation. The interrupt does not need to be

enabled, but the pin must be configured as a special-function input. If the EXTINTx

interrupt is enabled, the CPU executes the interrupt service routine. Otherwise, the

CPU executes the instruction that immediately follows the command that invoked

the power-saving mode.

In idle mode, asserting any enabled interrupt causes the device to resume normal

operation.

EXTINT0 shares a package pin with P2.2, EXTINT1 shares a package pin with

P2.4, EXTINT2 shares a package pin with P3.6, and EXTINT3 shares a package

pin with P3.7.

O Bus Hold Acknowledge

This active-low output indicates that the CPU has released the bus as the result of

an external device asserting HOLD#. When the bus-hold protocol is enabled

(WSR.7 is set), the P2.6/HLDA# pin can function only as HLDA#, regardless of the

configuration selected through the port configuration registers (P2_MODE,

P2_DIR, and P2_REG). An attempt to change the pin configuration is ignored until

the bus-hold protocol is disabled (WSR.7 is cleared).

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