8XL196NP データシートの表示（PDF） - Intel

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8XL196NP

COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Intel 

8XL196NP COMMERCIAL CHMOS 16-BIT MICROCONTROLLER

Name

RXD

T1CLK

T2CLK

T1DIR

T2DIR

TXD

VCC

VSS

WR#

Table 6. Signal Descriptions (Continued)

Type

Description

I/O Receive Serial Data

In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it functions as

either an input or an open-drain output for data.

RXD shares a package pin with P2.1.

I Timer 1 External Clock

External clock for timer 1. Timer 1 increments (or decrements) on both rising and

falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature

counting mode.

and

External clock for the serial I/O baud-rate generator input (program selectable).

T1CLK shares a package pin with P1.4.

I Timer 2 External Clock

External clock for timer 2. Timer 2 increments (or decrements) on both rising and

falling edges of T2CLK. It is also used in conjunction with T2DIR for quadrature

counting mode.

T2CLK shares a package pin with P1.6.

I Timer 1 External Direction

External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high

and decrements when it is low. Also used in conjunction with T1CLK for quadrature

counting mode.

T1DIR shares a package pin with P1.5.

I Timer 2 External Direction

External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high

and decrements when it is low. It is also used in conjunction with T2CLK for

quadrature counting mode.

T2DIR shares a package pin with P1.7.

O Transmit Serial Data

In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it

is the serial clock output.

TXD shares a package pin with P2.0.

PWR

GND

O

Digital Supply Voltage

Connect each VCC pin to the digital supply voltage.

Digital Circuit Ground

These pins supply ground for the digital circuitry. Connect each VSS pin to ground

through the lowest possible impedance path.

Write†

This active-low output indicates that an external write is occurring. This signal is

asserted only during external memory writes.

WR# shares a package pin with WRL#.

† When this pin is configured as a special-function signal (P5_MODE.2 = 1), the

chip configuration register 0 (CCR0) determines whether it functions as WR# or

WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.

15

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