UDA1360 データシートの表示（PDF） - Philips Electronics

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UDA1360

Low-voltage low-power stereo audio ADC

Philips Electronics 

Philips Semiconductors

Low-voltage low-power stereo audio ADC

Product specification

UDA1360TS

PINNING

SYMBOL

VINL

Vref

VINR

Vref(n)

Vref(p)

SFOR

PWON

SYSCLK

VDDD

VSSD

BCK

WS

DATAO

FSEL

VSSA

VDDA

PIN

DESCRIPTION

1 left channel input

2 reference voltage

3 right channel input

4 ADC negative reference voltage

5 ADC positive reference voltage

6 data format selection input

7 power control input

8 system clock input 256 or 384fs

9 digital supply voltage

10 digital ground

11 bit clock input

12 word selection input

13 data output

14 system clock frequency select

15 analog ground

16 analog supply voltage

handbook, halfpage

VINL 1

Vref 2

VINR 3

16 VDDA

15 VSSA

14 FSEL

Vref(n) 4

13 DATAO

UDA1360TS

Vref(p) 5

12 WS

SFOR 6

11 BCK

PWON 7

SYSCLK 8

10 VSSD

9 VDDD

MGM968

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

System clock

The UDA1360TS accommodates slave mode only, this

means that in all applications the system devices must

provide the system clock. The system frequency is

selectable via the static FSEL pin, and the system clock

must be locked in frequency to the digital interface input

signals.

The options are 256fs (FSEL = LOW) and 384fs

(FSEL = HIGH). The sampling frequency range is

5 to 55 kHz.

The BCK clock can be up to 128fs, or in other words the

BCK frequency is 128 times the Word Select (WS)

frequency or less: fBCK ≤ 128 × fWS.

Notes:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O

data interface.

2. For MSB justified formats it is important to have a WS

signal with 50% duty factor.

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1360TS consists of two

3rd-order Sigma-Delta modulators. They have a modified

Ritchie-coder architecture in a differential switched

capacitor implementation. The over-sampling ratio is 128.

Input level

The overall system gain is proportional to VDDA. The 0 dB

input level is defined as that which gives a −1 dB FS digital

output (relative to the full-scale swing). In addition, an input

gain switch is incorporated with the above definitions.

The UDA1360TS front-end is equipped with a selectable

0 or 6 dB gain, in order to supports 2 V (RMS) input using

a series resistor of 12 kΩ.

For the definition of the pin settings for 1 or 2 V (RMS)

mode given in Table 1, it is assumed that this resistor is

present as a default component.

If the 2 V (RMS) signal input is not needed, the external

resistor should not be used.

2001 Mar 14

4

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