UPD750064A データシートの表示（PDF） - NEC => Renesas Technology

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UPD750064A

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Figure 6-1. Clock Generator Block Diagram

XT1

Subsystem

fXT

clock oscillator

XT2

X1

Main system fX

clock oscillator

X2

Watch timer

· Basic interval timer (BT)

· Timer/event counter

· Serial interface

· Watch timer

· INT0 noise eliminator

· Clock output circuit

1/1 to 1/4096

1/2 1/4 1/16

Divider

WM.3

SCC

SCC3

SCC0

PCC

PCC0

PCC1

4

PCC2

HALTNote

PCC3

STOPNote

Oscillation

stop

Selector

Selector

Divider

1/4

Φ

· CPU

· INT0 noise eliminator

· Clock output circuit

HALT F/F

S

RQ

PCC2,

PCC3

Clear

STOP F/F

QS

R

Wait release signal from BT

RESET signal

Standby release signal from

interrupt control circuit

Note Instruction execution

Remarks 1.

2.

3.

4.

5.

6.

fX = Main system clock frequency

fXT = Subsystem clock frequency

Φ = CPU clock

PCC: Processor Clock Control Register

SCC: System Clock Control Register

One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.

24

Data Sheet U10165EJ2V0DS00

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