UPD750064A データシートの表示（PDF） - NEC => Renesas Technology
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UPD750064A Datasheet PDF : 82 Pages
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µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)
6.6 Watch Timer
The µPD750068 has one channel of watch timer. The watch timer has the following functions.
(a) Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW.
(b) 0.5 sec interval can be created by both the main system clock (4.194304 MHz) and subsystem clock (32.768
kHz).
(c) Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the
fast feed mode.
(d) Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming
of system clock frequencies.
(e) Clears the frequency divider to make the clock start with zero seconds.
(f) Uses the clock of 0.5 sec as the clock source of the timer/event counter to continue the standby mode until
the longest time 9 hours (by using timer 0, 1) to be in the lowest consumption mode.
From
clock
generator
fX
128
(32.768 kHz)
fXT
(32.768 kHz)
Figure 6-5. Watch Timer Block Diagram
fW
27
(256 Hz : 3.91 ms)
fW
(32.768 kHz)
Selector
Divider
4 kHz 2 kHz
fW fW
23 24
Clear
fW
214
2 Hz
0.5 sec
Selector
INTW
IRQW
set signal
Selector
Output buffer
P23/BUZ
WM
WM7 0 WM5 WM4 WM3 WM2 WM1 WM0
PORT2.3
P23
output latch
PMGB bit 2
Port 2 input/
output mode
8
Bit test instruction
Internal bus
Remark The values enclosed in parentheses are applied when fX = 4.194304 MHz and fXT = 32.768 kHz.
28
Data Sheet U10165EJ2V0DS00
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