UPD750064A データシートの表示（PDF） - NEC => Renesas Technology

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UPD750064A

4 BIT SINGLE CHIP CMOS MICROCOMPUTERS

NEC => Renesas Technology 

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

6.4 Clock Output Circuit

The clock output circuit is provided to output the clock pulses from the P22/PCL pin to the remote control wave

output applications and peripheral LSIs.

• Clock output (PCL) : Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19-MHz operation)

: Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0-MHz operation)

From clock

generator

Φ

fX/22

fX/24

fX/26

Figure 6-3. Clock Output Circuit Block Diagram

Selector

Output buffer

PCL/P22

CLOM3 0 CLOM1 CLOM0 CLOM

PORT2.2

P22

output latch

Bit 2 of PMGB

Port 2 I/O mode

specification bit

4

Internal bus

Remark Special care has been taken in designing the chip so that small-width pulses may not be output

when switching clock output enable/disable.

26

Data Sheet U10165EJ2V0DS00

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