W742C814 データシートの表示（PDF） - Winbond

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W742C814

4-BIT MICROCONTROLLER

Winbond 

W742C814

The organization of the dual-clock operation mode is shown in Figure 6-4.

X IN

XOUT

STOP

SC R .0

HOLD

F s lo w

O scillator

Fslow Ffast

Fosc

System Clock

T1

T2

G enerator

T3

T4

PLL

D ivider 0

SC R .1

enable/disable

Fslow

Fslow

LCD Frequency

Selector

Flcd

D ivider 1

IN T4

H C F.4

SC R .3 (14/12 bit)

SCR : System clock Control Register (default = 00h )

B it3

Bit1 Bit0

0 : Fosc = Fslow

1 : Fosc = Ffast

0 : PLL disable

1 : PLL enable

D ual clock operation m ode :

0 : 14 bit

1 : 12 bit

- SC R .0=0, Fosc=Fslow ; SC R .0=1, Fosc=Ffast

- In STO P m ode LCD is turned off

- SCR value w ill be reset as X X 00B after w akeup from STO P m ode

Figure 6-4 Organization of the dual-clock operation mode

6.10 WatchDog Timer (WDT) and WatchDog Timer Register (WDTR)

The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from

unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled,

and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is

FOSC/2048. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/2048) by setting

WDTR.3 to 1. The contents of the WDT can be reset by the instruction CLR WDT. In normal

operation, the application program must reset WDT before it overflows. A WDT overflow indicates that

operation is not under control and the chip will be reset. The WDT overflow period is 1 S when the

sub-system clock (Fslow) is 32 KHz and WDT clock input is Fslow/2048. When the corresponding

option code bit of the WDT set to 0, the WDT function is disabled. The organization of the Divider0

and watchdog timer is shown in Figure 6-5.

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Publication Release Date: February 12, 2003

Revision A2

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