AD1955 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD1955 Datasheet PDF : 10 Pages
| |||
PRELIMINARY TECHNICAL DATA
AD1955
PIN FUNCTION DESCRIPTIONS
Pin
I/O Pin Name
Description
1
DVDD
Digital Power Supply Connected to Digital 5V supply.
2
Input EF_WCLK/LRCLK Word Clock in External Filter mode.
Left/Right Clock input for input data in PCM mode.
3
Input EF_BCLK/BCLK
Bit Clock input in External Filter mode. Bit Clock input for input data in PCM mode.
4
Input EF_LDATA/SDATA 8fs or 4fs L-ch Data input in External filter mode. Data should be MSB first two’s
complement format. In the PCM mode, serial input, MSB first, containing two
channels(left and right) of 16 to 24bit two’s complement 1fs data.
5
Input EF_RDATA
8fs or 4fs R-ch Data input in External filter mode. Data should be MSB first two’s
complement format. Not used in PCM mode
6
I/O DSD_SCLK
Shift clock input for DSD data. This clock should be 64x44.1kHz, 2.8224MHz or
128x44.1kHz, 5.6448MHz in normal mode or 128x44.1kHz, 5.6448MHz or
256x44.1kHz, 11.2896MHz in phase mode.
7
Input DSD_LDATA
DSD Left channel data input
8
Input DSD_RDATA
DSD Right channel data input
9
I/O DSD_PHASE
DSD phase reference signal. This clock should be 64x44.1kHz, 2.8224MHz. If not
used this pin should be connected Low.
10
AGND
Analog Ground
11 Output IOUTR+
Right Channel Positive analog output.
12 Output IOUTR-
Right Channel Negative analog output.
13 Output FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage
reference with parallel 10uF and 0.1uF capacitors to AGND
14
IREF
Connection point for external bias resistor.
15
AVDD
Analog power supply Connected to Analog 5V supply
16 Output FILTB
Filter Capacitor Connection with parallel 10uF and 0.1uF capacitors to AGND
17 Output IOUTL-
Left Channel Negative analog output.
18 Output IOUTL+
Left Channel Positive analog output.
19
AGND
Analog Ground
20 Output ZEROR
Right Channel Zero Flag Output. This pin goes high when the right channel has no
signal input or the DSD mute pattern is detected.
21 Output ZEROL
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal
input or the DSD mute pattern is detected.
22
Input MUTE
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal
operation.
23
Input PD/RST
Power down/Reset. The AD1955 is placed in a reset state and the digital circuitry is
powered down when this pin is held LO. The AD1955 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values. Connect HI
for normal operation.
24
Input CDATA
Serial control input, MSB first, containing 16 bits of unsigned data. Used for
specifying control information and channel-specific attenuation.
25
Input CLATCH
Latch Input for control data.
26
Input CCLK
Control Clock input for control data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
27
Input MCLK
Master Clock Input. Connect to an external clock source.
28
DGND
Digital Ground
Rev. PrF
-5-
Share Link: 