T431616A データシートの表示（PDF） - Taiwan Memory Technology

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メーカー

T431616A

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616A

Read & Write Cycle at Same Bank @Burst Length = 4

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

tR C D

tR C

*N ote1

H IG H

*N ote2

ADDR

Ra

C a0

Rb

C b0

BA

A 10/A P

Ra

CL=2

DQ

CL=3

WE

tR A C

*N ote3

*N ote3

Rb

tO H

Q a0 Q a1 Q a2 Q a3

tSA C

tO H

tSH Z

*N ote4

Q a0 Q a1 Q a2 Q a3

tSA C

tSH Z

*N ote4

Db0 Db1 Db2 Db3

tR D L

Db0 Db1 Db2 Db3

tR D L

DQM

Row

A ctiv e (A -

B ank)

R ead (A -

B ank)

P recharg

e (A -

B ank)

R o w A ctiv e

(A -B nak)

W rite (A -

B nak)

P recharge

(a-B nak)

:D o n 't c a re

*Note : 1. Minimum row cycle times is requiqed to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is

available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock.

3. Access time from Row active command. tCC*(tRCD+CAS latency-1)+tSAC

4. Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)

Burst can’t end in Full Page Mode.

Taiwan Memory Technology, Inc. reserves the right P.17

to change products or specifications without notice.

Publication Date: DEC. 2000

Revision: C

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