AD9870 データシートの表示（PDF） - Analog Devices
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AD9870 Datasheet PDF : 20 Pages
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AD9870–SPECIFICATIONS (VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ =
VDDP = 5.0 V, CLK = 18 MSPS, FIF = 73.35 MHz, FLO = 71.1 MHz, unless otherwise noted.)
Parameter
Conditions1
Min Typ
Max
Unit
OVERALL
Analog Supply Voltage
(VDDA, VDDF, VDDI)
Digital Supply Voltage
(VDDD, VDDC, VDDL)
Interface Supply Voltage
(VDDH)
Charge Pump Supply Voltage
(VDDP, VDDQ)
Total Current
SSB Noise Figure @ Max VGA Gain
Input Third-Order Intercept (IIP3)
Input Impedance
Gain Variation Over Temperature
High IIP3 Setting
High IIP3 Setting
Low IIP3 Setting
High IIP3 Setting
Low IIP3 Setting
2.7
3.0
3.6
2.7
3.0
3.6
1.8
3.6
2.7
3.0
5.5
42
50.6
12
12
–5
–1
–10
360
0.6
V
V
V
V
mA
dB
dB
dBm
dBm
Ω
dB
PREAMP + MIXER
Maximum Input and LO Frequencies
300
MHz
LO SYNTHESIZER
LO Input Frequency
LO Input Amplitude
FREF (Reference) Frequency
FREF Input Amplitude
Minimum Charge Pump Output Current
Maximum Charge Pump Output Current
Charge Pump Output Compliance Voltage2
Synthesizer Resolution
Programmable in 0.625 mA Steps
Programmable in 0.625 mA Steps
7.75
0.3
0.1
0.3
0.625
5.000
0.25
6.25
300
1.0
25
3
VDDP – 0.25
MHz
V p-p
MHz
V p-p
mA
mA
V
kHz
CLOCK SYNTHESIZER
CLK Input Frequency
CLK Input Amplitude
Minimum Charge Pump Output Current
Maximum Charge Pump Output Current
Charge Pump Output Compliance Voltage2
Synthesizer Resolution
Clock VCO Off
Programmable in 0.625 mA Steps
Programmable in 0.625 mA Steps
13
0.3
0.625
5.000
0.25
2.2
18
VDDQ – 0.25
MHz
V p-p
mA
mA
V
kHz
SIGMA-DELTA ADC
Resolution
Clock Frequency (fCLK)
Center Frequency
Dynamic Range
Passband Gain Variation
BW = 10 kHz
16
13
18
fCLK/8
88
0.5
Bits
MHz
MHz
dB
dB
DECIMATOR
Decimation Factor
Passband Width
Passband Gain Variation
Alias Attenuation
Programmable in Steps of 60
60
960
50
%
1
dB
85
dB
GAIN CONTROL
Programmable Gain Step
AGC Gain Range (Continuous)
AGC Attack Time
Programmable
16
dB
18
25
60
dB
40
7000
µs
SPI
PC Clock Frequency
PD Hold Time
10
MHz
10
ns
SSI
CLKOUT Frequency
Output Rise/Fall Time
1
CMOS Output Mode, Drive Strength = 0
CMOS Output Mode, Drive Strength = 1
CMOS Output Mode, Drive Strength = 2
CMOS Output Mode, Drive Strength = 3
18
MHz
120
ns
45
ns
16
ns
10
ns
OPERATING TEMPERATURE RANGE
Basic Functions
Meets All Specifications
–40
+95
°C
–40
+85
°C
NOTES
1Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, 25 pF load on SSI output pins: VDDx = 3.0 V.
2Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
Specifications subject to change without notice.
–2–
REV. 0
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