NAND04GW3C2N1E データシートの表示（PDF） - STMicroelectronics

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NAND04GW3C2N1E

4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory

STMicroelectronics 

6 Device operations

NAND04GA3C2A, NAND04GW3C2A

6.6

Sequential Input

To input data sequentially the addresses must be sequential and remain in one block.

For Sequential Input each Page Program operation comprises five steps:

1. One bus cycle is required to setup the Page Program (Sequential Input) command (see

Table 8).

2. Five bus cycles are then required to input the program address (refer to Table 6).

3. The data is then loaded into the Data Registers.

4. One bus cycle is required to issue the Page Program confirm command to start the

P/E/R Controller. The P/E/R will only start if the data has been loaded in step 3.

5. The P/E/R Controller then programs the data into the array.

6.7

Random Data input

During a Sequential Input operation, the next sequential address to be programmed can be

replaced by a random address, by issuing a Random Data Input command. The following

two steps are required to issue the command:

1. One bus cycle is required to setup the Random Data Input command (see Table 8).

2. Two bus cycles are then required to input the new column address (refer to Table 6).

Random Data Input can be repeated as often as required in any given page.

Once the program operation has started the Status Register can be read using the Read

Status Register command. During program operations the Status Register will only flag

errors for bits set to '1' that have not been successfully programmed to '0'.

During the program operation, only the Read Status Register and Reset commands will be

accepted, all other commands will be ignored.

Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the

Ready/Busy signal goes High.

The device remains in Read Status Register mode until another valid command is written to

the Command Interface.

Figure 8. Page Program Operation

RB

I/O

80h

Page Program

Setup Code

Address Inputs

tBLBH2

(Program Busy time)

Data Input

10h

Confirm

Code

Busy

70h SR0

Read Status Register

ai08659

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